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@@ -39,18 +39,16 @@ static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
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#define GPTPR_PRESCALER24M_SHIFT 12
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#define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT)
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+DECLARE_GLOBAL_DATA_PTR;
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+
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static inline int gpt_has_clk_source_osc(void)
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{
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-#if defined(CONFIG_MX6)
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if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) ||
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is_mx6dqp() || is_mx6sdl() || is_mx6sx() || is_mx6ul() ||
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- is_mx6ull() || is_mx6sll())
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+ is_mx6ull() || is_mx6sll() || is_mx7())
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return 1;
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return 0;
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-#else
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- return 0;
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-#endif
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}
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static inline ulong gpt_get_clk(void)
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@@ -73,7 +71,8 @@ int timer_init(void)
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__raw_writel(GPTCR_SWR, &cur_gpt->control);
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/* We have no udelay by now */
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- __raw_writel(0, &cur_gpt->control);
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+ for (i = 0; i < 100; i++)
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+ __raw_writel(0, &cur_gpt->control);
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i = __raw_readl(&cur_gpt->control);
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i &= ~GPTCR_CLKSOURCE_MASK;
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@@ -87,7 +86,7 @@ int timer_init(void)
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* Enable bit and prescaler
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*/
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if (is_mx6sdl() || is_mx6sx() || is_mx6ul() || is_mx6ull() ||
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- is_mx6sll()) {
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+ is_mx6sll() || is_mx7()) {
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i |= GPTCR_24MEN;
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/* Produce 3Mhz clock */
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@@ -103,6 +102,9 @@ int timer_init(void)
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#endif
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__raw_writel(i, &cur_gpt->control);
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+ gd->arch.tbl = __raw_readl(&cur_gpt->counter);
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+ gd->arch.tbu = 0;
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+
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return 0;
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}
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