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arm: Remove zmx25 board and ARCH_MX25

This board has not been converted to CONFIG_DM by the deadline.
Remove it.  As this is the last ARCH_MX25 platform, remove those
references as well.

Cc: Matthias Weisser <weisserm@arcor.de>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini 2 years ago
parent
commit
8ba59608dc

+ 0 - 9
arch/arm/Kconfig

@@ -854,13 +854,6 @@ config ARCH_MX23
 	select PL011_SERIAL
 	select SUPPORT_SPL
 
-config ARCH_MX25
-	bool "NXP MX25"
-	select CPU_ARM926EJS
-	select GPIO_EXTRA_HEADER
-	select MACH_IMX
-	imply MXC_GPIO
-
 config ARCH_MX28
 	bool "NXP i.MX28 family"
 	select CPU_ARM926EJS
@@ -2057,8 +2050,6 @@ source "arch/arm/mach-octeontx2/Kconfig"
 
 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
 
-source "arch/arm/mach-imx/mx2/Kconfig"
-
 source "arch/arm/mach-imx/mx3/Kconfig"
 
 source "arch/arm/mach-imx/mx5/Kconfig"

+ 0 - 1
arch/arm/cpu/arm926ejs/Makefile

@@ -12,7 +12,6 @@ extra-y	:=
 endif
 endif
 
-obj-$(CONFIG_MX25) += mx25/
 obj-$(CONFIG_MX27) += mx27/
 obj-$(if $(filter mxs,$(SOC)),y) += mxs/
 obj-$(if $(filter spear,$(SOC)),y) += spear/

+ 0 - 7
arch/arm/cpu/arm926ejs/mx25/Makefile

@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-
-obj-y	+= generic.o timer.o reset.o relocate.o

+ 0 - 274
arch/arm/cpu/arm926ejs/mx25/generic.c

@@ -1,274 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2009 DENX Software Engineering
- * Author: John Rigby <jrigby@gmail.com>
- *
- * Based on mx27/generic.c:
- *  Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
- *  Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
- */
-
-#include <common.h>
-#include <clock_legacy.h>
-#include <div64.h>
-#include <init.h>
-#include <net.h>
-#include <netdev.h>
-#include <vsprintf.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/arch-imx/cpu.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/clock.h>
-
-#ifdef CONFIG_FSL_ESDHC_IMX
-#include <fsl_esdhc_imx.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
-/*
- *  get the system pll clock in Hz
- *
- *                  mfi + mfn / (mfd +1)
- *  f = 2 * f_ref * --------------------
- *                        pd + 1
- */
-static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
-{
-	unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
-	    & CCM_PLL_MFI_MASK;
-	int mfn = (pll >> CCM_PLL_MFN_SHIFT)
-	    & CCM_PLL_MFN_MASK;
-	unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
-	    & CCM_PLL_MFD_MASK;
-	unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
-	    & CCM_PLL_PD_MASK;
-
-	mfi = mfi <= 5 ? 5 : mfi;
-	mfn = mfn >= 512 ? mfn - 1024 : mfn;
-	mfd += 1;
-	pd += 1;
-
-	return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn),
-		     mfd * pd);
-}
-
-static ulong imx_get_mpllclk(void)
-{
-	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong fref = MXC_HCLK;
-
-	return imx_decode_pll(readl(&ccm->mpctl), fref);
-}
-
-static ulong imx_get_upllclk(void)
-{
-	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong fref = MXC_HCLK;
-
-	return imx_decode_pll(readl(&ccm->upctl), fref);
-}
-
-static ulong imx_get_armclk(void)
-{
-	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong cctl = readl(&ccm->cctl);
-	ulong fref = imx_get_mpllclk();
-	ulong div;
-
-	if (cctl & CCM_CCTL_ARM_SRC)
-		fref = lldiv((u64) fref * 3, 4);
-
-	div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
-	       & CCM_CCTL_ARM_DIV_MASK) + 1;
-
-	return fref / div;
-}
-
-static ulong imx_get_ahbclk(void)
-{
-	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong cctl = readl(&ccm->cctl);
-	ulong fref = imx_get_armclk();
-	ulong div;
-
-	div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
-	       & CCM_CCTL_AHB_DIV_MASK) + 1;
-
-	return fref / div;
-}
-
-static ulong imx_get_ipgclk(void)
-{
-	return imx_get_ahbclk() / 2;
-}
-
-static ulong imx_get_perclk(int clk)
-{
-	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() :
-						     imx_get_ahbclk();
-	ulong div;
-
-	div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
-	div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
-
-	return fref / div;
-}
-
-int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq)
-{
-	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong fref = from_upll ? imx_get_upllclk() : imx_get_ahbclk();
-	ulong div = (fref + freq - 1) / freq;
-
-	if (clk > MXC_UART_CLK || !div || --div > CCM_PERCLK_MASK)
-		return -EINVAL;
-
-	clrsetbits_le32(&ccm->pcdr[CCM_PERCLK_REG(clk)],
-			CCM_PERCLK_MASK << CCM_PERCLK_SHIFT(clk),
-			div << CCM_PERCLK_SHIFT(clk));
-	if (from_upll)
-		setbits_le32(&ccm->mcr, 1 << clk);
-	else
-		clrbits_le32(&ccm->mcr, 1 << clk);
-	return 0;
-}
-
-unsigned int mxc_get_clock(enum mxc_clock clk)
-{
-	if (clk >= MXC_CLK_NUM)
-		return -1;
-	switch (clk) {
-	case MXC_ARM_CLK:
-		return imx_get_armclk();
-	case MXC_AHB_CLK:
-		return imx_get_ahbclk();
-	case MXC_IPG_CLK:
-	case MXC_CSPI_CLK:
-	case MXC_FEC_CLK:
-		return imx_get_ipgclk();
-	default:
-		return imx_get_perclk(clk);
-	}
-}
-
-u32 get_cpu_rev(void)
-{
-	u32 srev;
-	u32 system_rev = 0x25000;
-
-	/* read SREV register from IIM module */
-	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
-	srev = readl(&iim->iim_srev);
-
-	switch (srev) {
-	case 0x00:
-		system_rev |= CHIP_REV_1_0;
-		break;
-	case 0x01:
-		system_rev |= CHIP_REV_1_1;
-		break;
-	case 0x02:
-		system_rev |= CHIP_REV_1_2;
-		break;
-	default:
-		system_rev |= 0x8000;
-		break;
-	}
-
-	return system_rev;
-}
-
-#if defined(CONFIG_DISPLAY_CPUINFO)
-static char *get_reset_cause(void)
-{
-	/* read RCSR register from CCM module */
-	struct ccm_regs *ccm =
-		(struct ccm_regs *)IMX_CCM_BASE;
-
-	u32 cause = readl(&ccm->rcsr) & 0x0f;
-
-	if (cause == 0)
-		return "POR";
-	else if (cause == 1)
-		return "RST";
-	else if ((cause & 2) == 2)
-		return "WDOG";
-	else if ((cause & 4) == 4)
-		return "SW RESET";
-	else if ((cause & 8) == 8)
-		return "JTAG";
-	else
-		return "unknown reset";
-
-}
-
-int print_cpuinfo(void)
-{
-	char buf[32];
-	u32 cpurev = get_cpu_rev();
-
-	printf("CPU:   Freescale i.MX25 rev%d.%d%s at %s MHz\n",
-		(cpurev & 0xF0) >> 4, (cpurev & 0x0F),
-		((cpurev & 0x8000) ? " unknown" : ""),
-		strmhz(buf, imx_get_armclk()));
-	printf("Reset cause: %s\n", get_reset_cause());
-	return 0;
-}
-#endif
-
-#if defined(CONFIG_FEC_MXC)
-/*
- * Initializes on-chip ethernet controllers.
- * to override, implement board_eth_init()
- */
-int cpu_eth_init(struct bd_info *bis)
-{
-	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong val;
-
-	val = readl(&ccm->cgr0);
-	val |= (1 << 23);
-	writel(val, &ccm->cgr0);
-	return fecmxc_initialize(bis);
-}
-#endif
-
-int get_clocks(void)
-{
-#ifdef CONFIG_FSL_ESDHC_IMX
-#if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
-	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-#else
-	gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
-#endif
-#endif
-	return 0;
-}
-
-#ifdef CONFIG_FSL_ESDHC_IMX
-/*
- * Initializes on-chip MMC controllers.
- * to override, implement board_mmc_init()
- */
-int cpu_mmc_init(struct bd_info *bis)
-{
-	return fsl_esdhc_mmc_init(bis);
-}
-#endif
-
-#ifdef CONFIG_FEC_MXC
-void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
-{
-	int i;
-	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
-	struct fuse_bank *bank = &iim->bank[0];
-	struct fuse_bank0_regs *fuse =
-			(struct fuse_bank0_regs *)bank->fuse_regs;
-
-	for (i = 0; i < 6; i++)
-		mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
-}
-#endif /* CONFIG_FEC_MXC */

+ 0 - 22
arch/arm/cpu/arm926ejs/mx25/relocate.S

@@ -1,22 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *  relocate - i.MX25-specific vector relocation
- *
- *  Copyright (c) 2013  Albert ARIBAUD <albert.u.boot@aribaud.net>
- */
-
-#include <linux/linkage.h>
-
-/*
- * The i.MX25 SoC is very specific with respect to exceptions: it
- * does not provide RAM at the high vectors address (0xFFFF0000),
- * thus only the low address (0x00000000) is useable; but that is
- * in ROM, so let's avoid relocating the vectors.
- */
-	.section	.text.relocate_vectors,"ax",%progbits
-
-ENTRY(relocate_vectors)
-
-	bx	lr
-
-ENDPROC(relocate_vectors)

+ 0 - 40
arch/arm/cpu/arm926ejs/mx25/reset.c

@@ -1,40 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2009
- * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- */
-
-#include <common.h>
-#include <cpu_func.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-
-/*
- * Reset the cpu by setting up the watchdog timer and let it time out
- */
-void reset_cpu(void)
-{
-	struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
-	/* Disable watchdog and set Time-Out field to 0 */
-	writew(0, &regs->wcr);
-
-	/* Write Service Sequence */
-	writew(WSR_UNLOCK1, &regs->wsr);
-	writew(WSR_UNLOCK2, &regs->wsr);
-
-	/* Enable watchdog */
-	writew(WCR_WDE, &regs->wcr);
-
-	while (1) ;
-}

+ 0 - 50
arch/arm/cpu/arm926ejs/mx25/timer.c

@@ -1,50 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
- *
- * (C) Copyright 2009
- * Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- *
- * (C) Copyright 2009 DENX Software Engineering
- * Author: John Rigby <jrigby@gmail.com>
- *	Add support for MX25
- */
-
-#include <common.h>
-#include <init.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/ptrace.h>
-
-/* nothing really to do with interrupts, just starts up a counter. */
-/* The 32KHz 32-bit timer overruns in 134217 seconds */
-int timer_init(void)
-{
-	int i;
-	struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
-	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-
-	/* setup GP Timer 1 */
-	writel(GPT_CTRL_SWR, &gpt->ctrl);
-
-	writel(readl(&ccm->cgr1) | CCM_CGR1_GPT1, &ccm->cgr1);
-
-	for (i = 0; i < 100; i++)
-		writel(0, &gpt->ctrl); /* We have no udelay by now */
-	writel(0, &gpt->pre); /* prescaler = 1 */
-	/* Freerun Mode, 32KHz input */
-	writel(readl(&gpt->ctrl) | GPT_CTRL_CLKSOURCE_32 | GPT_CTRL_FRR,
-			&gpt->ctrl);
-	writel(readl(&gpt->ctrl) | GPT_CTRL_TEN, &gpt->ctrl);
-
-	return 0;
-}

+ 0 - 57
arch/arm/include/asm/arch-mx25/clock.h

@@ -1,57 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- *
- * (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
- *
- * Modified for mx25 by John Rigby <jrigby@gmail.com>
- */
-
-#ifndef __ASM_ARCH_CLOCK_H
-#define __ASM_ARCH_CLOCK_H
-
-#ifdef CONFIG_MX25_HCLK_FREQ
-#define MXC_HCLK	CONFIG_MX25_HCLK_FREQ
-#else
-#define MXC_HCLK	24000000
-#endif
-
-#ifdef CONFIG_MX25_CLK32
-#define MXC_CLK32	CONFIG_MX25_CLK32
-#else
-#define MXC_CLK32	32768
-#endif
-
-enum mxc_clock {
-	/* PER clocks (do not change order) */
-	MXC_CSI_CLK,
-	MXC_EPIT_CLK,
-	MXC_ESAI_CLK,
-	MXC_ESDHC1_CLK,
-	MXC_ESDHC2_CLK,
-	MXC_GPT_CLK,
-	MXC_I2C_CLK,
-	MXC_LCDC_CLK,
-	MXC_NFC_CLK,
-	MXC_OWIRE_CLK,
-	MXC_PWM_CLK,
-	MXC_SIM1_CLK,
-	MXC_SIM2_CLK,
-	MXC_SSI1_CLK,
-	MXC_SSI2_CLK,
-	MXC_UART_CLK,
-	/* Other clocks */
-	MXC_ARM_CLK,
-	MXC_AHB_CLK,
-	MXC_IPG_CLK,
-	MXC_CSPI_CLK,
-	MXC_FEC_CLK,
-	MXC_CLK_NUM
-};
-
-int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq);
-unsigned int mxc_get_clock(enum mxc_clock clk);
-
-#define imx_get_uartclk()	mxc_get_clock(MXC_UART_CLK)
-#define imx_get_fecclk()	mxc_get_clock(MXC_FEC_CLK)
-
-#endif /* __ASM_ARCH_CLOCK_H */

+ 0 - 13
arch/arm/include/asm/arch-mx25/gpio.h

@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011
- * Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
- */
-
-
-#ifndef __ASM_ARCH_MX25_GPIO_H
-#define __ASM_ARCH_MX25_GPIO_H
-
-#include <asm/mach-imx/gpio.h>
-
-#endif

+ 0 - 504
arch/arm/include/asm/arch-mx25/imx-regs.h

@@ -1,504 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2009, DENX Software Engineering
- * Author: John Rigby <jcrigby@gmail.com
- *
- *   Based on arch-mx31/imx-regs.h
- *	Copyright (C) 2009 Ilya Yanok,
- *		Emcraft Systems <yanok@emcraft.com>
- *   and arch-mx27/imx-regs.h
- *	Copyright (C) 2007 Pengutronix,
- *		Sascha Hauer <s.hauer@pengutronix.de>
- *	Copyright (C) 2009 Ilya Yanok,
- *		Emcraft Systems <yanok@emcraft.com>
- */
-
-#ifndef _IMX_REGS_H
-#define _IMX_REGS_H
-
-#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
-#include <asm/types.h>
-
-/* Clock Control Module (CCM) registers */
-struct ccm_regs {
-	u32 mpctl;	/* Core PLL Control */
-	u32 upctl;	/* USB PLL Control */
-	u32 cctl;	/* Clock Control */
-	u32 cgr0;	/* Clock Gating Control 0 */
-	u32 cgr1;	/* Clock Gating Control 1 */
-	u32 cgr2;	/* Clock Gating Control 2 */
-	u32 pcdr[4];	/* PER Clock Dividers */
-	u32 rcsr;	/* CCM Status */
-	u32 crdr;	/* CCM Reset and Debug */
-	u32 dcvr0;	/* DPTC Comparator Value 0 */
-	u32 dcvr1;	/* DPTC Comparator Value 1 */
-	u32 dcvr2;	/* DPTC Comparator Value 2 */
-	u32 dcvr3;	/* DPTC Comparator Value 3 */
-	u32 ltr0;	/* Load Tracking 0 */
-	u32 ltr1;	/* Load Tracking 1 */
-	u32 ltr2;	/* Load Tracking 2 */
-	u32 ltr3;	/* Load Tracking 3 */
-	u32 ltbr0;	/* Load Tracking Buffer 0 */
-	u32 ltbr1;	/* Load Tracking Buffer 1 */
-	u32 pcmr0;	/* Power Management Control 0 */
-	u32 pcmr1;	/* Power Management Control 1 */
-	u32 pcmr2;	/* Power Management Control 2 */
-	u32 mcr;	/* Miscellaneous Control */
-	u32 lpimr0;	/* Low Power Interrupt Mask 0 */
-	u32 lpimr1;	/* Low Power Interrupt Mask 1 */
-};
-
-/* Enhanced SDRAM Controller (ESDRAMC) registers */
-struct esdramc_regs {
-	u32 ctl0;	/* control 0 */
-	u32 cfg0;	/* configuration 0 */
-	u32 ctl1;	/* control 1 */
-	u32 cfg1;	/* configuration 1 */
-	u32 misc;	/* miscellaneous */
-	u32 pad[3];
-	u32 cdly1;	/* Delay Line 1 configuration debug */
-	u32 cdly2;	/* delay line 2 configuration debug */
-	u32 cdly3;	/* delay line 3 configuration debug */
-	u32 cdly4;	/* delay line 4 configuration debug */
-	u32 cdly5;	/* delay line 5 configuration debug */
-	u32 cdlyl;	/* delay line cycle length debug */
-};
-
-/* General Purpose Timer (GPT) registers */
-struct gpt_regs {
-	u32 ctrl;	/* control */
-	u32 pre;	/* prescaler */
-	u32 stat;	/* status */
-	u32 intr;	/* interrupt */
-	u32 cmp[3];	/* output compare 1-3 */
-	u32 capt[2];	/* input capture 1-2 */
-	u32 counter;	/* counter */
-};
-
-/* Watchdog Timer (WDOG) registers */
-struct wdog_regs {
-	u16 wcr;	/* Control */
-	u16 wsr;	/* Service */
-	u16 wrsr;	/* Reset Status */
-	u16 wicr;	/* Interrupt Control */
-	u16 wmcr;	/* Misc Control */
-};
-
-/* IIM control registers */
-struct iim_regs {
-	u32 iim_stat;
-	u32 iim_statm;
-	u32 iim_err;
-	u32 iim_emask;
-	u32 iim_fctl;
-	u32 iim_ua;
-	u32 iim_la;
-	u32 iim_sdat;
-	u32 iim_prev;
-	u32 iim_srev;
-	u32 iim_prg_p;
-	u32 iim_scs0;
-	u32 iim_scs1;
-	u32 iim_scs2;
-	u32 iim_scs3;
-	u32 res1[0x1f1];
-	struct fuse_bank {
-		u32 fuse_regs[0x20];
-		u32 fuse_rsvd[0xe0];
-	} bank[3];
-};
-
-struct fuse_bank0_regs {
-	u32 fuse0_7[8];
-	u32 uid[8];
-	u32 fuse16_25[0xa];
-	u32 mac_addr[6];
-};
-
-struct fuse_bank1_regs {
-	u32 fuse0_21[0x16];
-	u32 usr5;
-	u32 fuse23_29[7];
-	u32 usr6[2];
-};
-
-/* Multi-Layer AHB Crossbar Switch (MAX) registers */
-struct max_regs {
-	u32 mpr0;
-	u32 pad00[3];
-	u32 sgpcr0;
-	u32 pad01[59];
-	u32 mpr1;
-	u32 pad02[3];
-	u32 sgpcr1;
-	u32 pad03[59];
-	u32 mpr2;
-	u32 pad04[3];
-	u32 sgpcr2;
-	u32 pad05[59];
-	u32 mpr3;
-	u32 pad06[3];
-	u32 sgpcr3;
-	u32 pad07[59];
-	u32 mpr4;
-	u32 pad08[3];
-	u32 sgpcr4;
-	u32 pad09[251];
-	u32 mgpcr0;
-	u32 pad10[63];
-	u32 mgpcr1;
-	u32 pad11[63];
-	u32 mgpcr2;
-	u32 pad12[63];
-	u32 mgpcr3;
-	u32 pad13[63];
-	u32 mgpcr4;
-};
-
-/* AHB <-> IP-Bus Interface (AIPS) */
-struct aips_regs {
-	u32 mpr_0_7;
-	u32 mpr_8_15;
-};
-/* LCD controller registers */
-struct lcdc_regs {
-	u32 lssar;	/* Screen Start Address */
-	u32 lsr;	/* Size */
-	u32 lvpwr;	/* Virtual Page Width */
-	u32 lcpr;	/* Cursor Position */
-	u32 lcwhb;	/* Cursor Width Height and Blink */
-	u32 lccmr;	/* Color Cursor Mapping */
-	u32 lpcr;	/* Panel Configuration */
-	u32 lhcr;	/* Horizontal Configuration */
-	u32 lvcr;	/* Vertical Configuration */
-	u32 lpor;	/* Panning Offset */
-	u32 lscr;	/* Sharp Configuration */
-	u32 lpccr;	/* PWM Contrast Control */
-	u32 ldcr;	/* DMA Control */
-	u32 lrmcr;	/* Refresh Mode Control */
-	u32 licr;	/* Interrupt Configuration */
-	u32 lier;	/* Interrupt Enable */
-	u32 lisr;	/* Interrupt Status */
-	u32 res0[3];
-	u32 lgwsar;	/* Graphic Window Start Address */
-	u32 lgwsr;	/* Graphic Window Size */
-	u32 lgwvpwr;	/* Graphic Window Virtual Page Width Regist */
-	u32 lgwpor;	/* Graphic Window Panning Offset */
-	u32 lgwpr;	/* Graphic Window Position */
-	u32 lgwcr;	/* Graphic Window Control */
-	u32 lgwdcr;	/* Graphic Window DMA Control */
-	u32 res1[5];
-	u32 lauscr;	/* AUS Mode Control */
-	u32 lausccr;	/* AUS mode Cursor Control */
-	u32 res2[31 + 64*7];
-	u32 bglut;	/* Background Lookup Table */
-	u32 gwlut;	/* Graphic Window Lookup Table */
-};
-
-/* Wireless External Interface Module Registers */
-struct weim_regs {
-	u32 cscr0u;	/* Chip Select 0 Upper Register */
-	u32 cscr0l;	/* Chip Select 0 Lower Register */
-	u32 cscr0a;	/* Chip Select 0 Addition Register */
-	u32 pad0;
-	u32 cscr1u;	/* Chip Select 1 Upper Register */
-	u32 cscr1l;	/* Chip Select 1 Lower Register */
-	u32 cscr1a;	/* Chip Select 1 Addition Register */
-	u32 pad1;
-	u32 cscr2u;	/* Chip Select 2 Upper Register */
-	u32 cscr2l;	/* Chip Select 2 Lower Register */
-	u32 cscr2a;	/* Chip Select 2 Addition Register */
-	u32 pad2;
-	u32 cscr3u;	/* Chip Select 3 Upper Register */
-	u32 cscr3l;	/* Chip Select 3 Lower Register */
-	u32 cscr3a;	/* Chip Select 3 Addition Register */
-	u32 pad3;
-	u32 cscr4u;	/* Chip Select 4 Upper Register */
-	u32 cscr4l;	/* Chip Select 4 Lower Register */
-	u32 cscr4a;	/* Chip Select 4 Addition Register */
-	u32 pad4;
-	u32 cscr5u;	/* Chip Select 5 Upper Register */
-	u32 cscr5l;	/* Chip Select 5 Lower Register */
-	u32 cscr5a;	/* Chip Select 5 Addition Register */
-	u32 pad5;
-	u32 wcr;	/* WEIM Configuration Register */
-};
-
-/* Multi-Master Memory Interface */
-struct m3if_regs {
-	u32 ctl;	/* Control Register */
-	u32 wcfg0;	/* Watermark Configuration Register 0 */
-	u32 wcfg1;	/* Watermark Configuration Register1 */
-	u32 wcfg2;	/* Watermark Configuration Register2 */
-	u32 wcfg3;	/* Watermark Configuration Register 3 */
-	u32 wcfg4;	/* Watermark Configuration Register 4 */
-	u32 wcfg5;	/* Watermark Configuration Register 5 */
-	u32 wcfg6;	/* Watermark Configuration Register 6 */
-	u32 wcfg7;	/* Watermark Configuration Register 7 */
-	u32 wcsr;	/* Watermark Control and Status Register */
-	u32 scfg0;	/* Snooping Configuration Register 0 */
-	u32 scfg1;	/* Snooping Configuration Register 1 */
-	u32 scfg2;	/* Snooping Configuration Register 2 */
-	u32 ssr0;	/* Snooping Status Register 0 */
-	u32 ssr1;	/* Snooping Status Register 1 */
-	u32 res0;
-	u32 mlwe0;	/* Master Lock WEIM CS0 Register */
-	u32 mlwe1;	/* Master Lock WEIM CS1 Register */
-	u32 mlwe2;	/* Master Lock WEIM CS2 Register */
-	u32 mlwe3;	/* Master Lock WEIM CS3 Register */
-	u32 mlwe4;	/* Master Lock WEIM CS4 Register */
-	u32 mlwe5;	/* Master Lock WEIM CS5 Register */
-};
-
-/* Pulse width modulation */
-struct pwm_regs {
-	u32 cr;	/* Control Register */
-	u32 sr;	/* Status Register */
-	u32 ir;	/* Interrupt Register */
-	u32 sar;	/* Sample Register */
-	u32 pr;	/* Period Register */
-	u32 cnr;	/* Counter Register */
-};
-
-/* Enhanced Periodic Interrupt Timer */
-struct epit_regs {
-	u32 cr;	/* Control register */
-	u32 sr;	/* Status register */
-	u32 lr;	/* Load register */
-	u32 cmpr;	/* Compare register */
-	u32 cnr;	/* Counter register */
-};
-
-#endif
-
-#define ARCH_MXC
-
-/* AIPS 1 */
-#define IMX_AIPS1_BASE		(0x43F00000)
-#define IMX_MAX_BASE		(0x43F04000)
-#define IMX_CLKCTL_BASE		(0x43F08000)
-#define IMX_ETB_SLOT4_BASE	(0x43F0C000)
-#define IMX_ETB_SLOT5_BASE	(0x43F10000)
-#define IMX_ECT_CTIO_BASE	(0x43F18000)
-#define I2C1_BASE_ADDR		(0x43F80000)
-#define I2C3_BASE_ADDR		(0x43F84000)
-#define IMX_CAN1_BASE		(0x43F88000)
-#define IMX_CAN2_BASE		(0x43F8C000)
-#define UART1_BASE		(0x43F90000)
-#define UART2_BASE		(0x43F94000)
-#define I2C2_BASE_ADDR		(0x43F98000)
-#define IMX_OWIRE_BASE		(0x43F9C000)
-#define IMX_CSPI1_BASE		(0x43FA4000)
-#define IMX_KPP_BASE		(0x43FA8000)
-#define IMX_IOPADMUX_BASE	(0x43FAC000)
-#define IOMUXC_BASE_ADDR	IMX_IOPADMUX_BASE
-#define IMX_IOPADCTL_BASE	(0x43FAC22C)
-#define IMX_IOPADGRPCTL_BASE	(0x43FAC418)
-#define IMX_IOPADINPUTSEL_BASE	(0x43FAC460)
-#define IMX_AUDMUX_BASE		(0x43FB0000)
-#define IMX_ECT_IP1_BASE	(0x43FB8000)
-#define IMX_ECT_IP2_BASE	(0x43FBC000)
-
-/* SPBA */
-#define IMX_SPBA_BASE		(0x50000000)
-#define IMX_CSPI3_BASE		(0x50004000)
-#define UART4_BASE		(0x50008000)
-#define UART3_BASE		(0x5000C000)
-#define IMX_CSPI2_BASE		(0x50010000)
-#define IMX_SSI2_BASE		(0x50014000)
-#define IMX_ESAI_BASE		(0x50018000)
-#define IMX_ATA_DMA_BASE	(0x50020000)
-#define IMX_SIM1_BASE		(0x50024000)
-#define IMX_SIM2_BASE		(0x50028000)
-#define UART5_BASE		(0x5002C000)
-#define IMX_TSC_BASE		(0x50030000)
-#define IMX_SSI1_BASE		(0x50034000)
-#define IMX_FEC_BASE		(0x50038000)
-#define IMX_SPBA_CTRL_BASE	(0x5003C000)
-
-/* AIPS 2 */
-#define IMX_AIPS2_BASE		(0x53F00000)
-#define IMX_CCM_BASE		(0x53F80000)
-#define IMX_GPT4_BASE		(0x53F84000)
-#define IMX_GPT3_BASE		(0x53F88000)
-#define IMX_GPT2_BASE		(0x53F8C000)
-#define IMX_GPT1_BASE		(0x53F90000)
-#define IMX_EPIT1_BASE		(0x53F94000)
-#define IMX_EPIT2_BASE		(0x53F98000)
-#define IMX_GPIO4_BASE		(0x53F9C000)
-#define IMX_PWM2_BASE		(0x53FA0000)
-#define IMX_GPIO3_BASE		(0x53FA4000)
-#define IMX_PWM3_BASE		(0x53FA8000)
-#define IMX_SCC_BASE		(0x53FAC000)
-#define IMX_SCM_BASE		(0x53FAE000)
-#define IMX_SMN_BASE		(0x53FAF000)
-#define IMX_RNGD_BASE		(0x53FB0000)
-#define IMX_MMC_SDHC1_BASE	(0x53FB4000)
-#define IMX_MMC_SDHC2_BASE	(0x53FB8000)
-#define IMX_LCDC_BASE		(0x53FBC000)
-#define IMX_SLCDC_BASE		(0x53FC0000)
-#define IMX_PWM4_BASE		(0x53FC8000)
-#define IMX_GPIO1_BASE		(0x53FCC000)
-#define IMX_GPIO2_BASE		(0x53FD0000)
-#define IMX_SDMA_BASE		(0x53FD4000)
-#define IMX_WDT_BASE		(0x53FDC000)
-#define WDOG1_BASE_ADDR	IMX_WDT_BASE
-#define IMX_PWM1_BASE		(0x53FE0000)
-#define IMX_RTIC_BASE		(0x53FEC000)
-#define IMX_IIM_BASE		(0x53FF0000)
-#define IIM_BASE_ADDR		IMX_IIM_BASE
-#define IMX_USB_BASE		(0x53FF4000)
-/*
- * This is in contradiction to the imx25 reference manual, which says that
- * port 1's registers start at 0x53FF4200. The correct base address for
- * port 1 is 0x53FF4400. The kernel uses 0x53FF4400 as well.
- */
-#define IMX_USB_PORT_OFFSET	0x400
-#define IMX_CSI_BASE		(0x53FF8000)
-#define IMX_DRYICE_BASE		(0x53FFC000)
-
-#define IMX_ARM926_ROMPATCH	(0x60000000)
-#define IMX_ARM926_ASIC		(0x68000000)
-
-/* 128K Internal Static RAM */
-#define IMX_RAM_BASE		(0x78000000)
-#define IMX_RAM_SIZE		(128 * 1024)
-
-/* SDRAM BANKS */
-#define IMX_SDRAM_BANK0_BASE	(0x80000000)
-#define IMX_SDRAM_BANK1_BASE	(0x90000000)
-
-#define IMX_WEIM_CS0		(0xA0000000)
-#define IMX_WEIM_CS1		(0xA8000000)
-#define IMX_WEIM_CS2		(0xB0000000)
-#define IMX_WEIM_CS3		(0xB2000000)
-#define IMX_WEIM_CS4		(0xB4000000)
-#define IMX_ESDRAMC_BASE	(0xB8001000)
-#define IMX_WEIM_CTRL_BASE	(0xB8002000)
-#define IMX_M3IF_CTRL_BASE	(0xB8003000)
-#define IMX_EMI_CTRL_BASE	(0xB8004000)
-
-/* NAND Flash Controller */
-#define IMX_NFC_BASE		(0xBB000000)
-#define NFC_BASE_ADDR		IMX_NFC_BASE
-
-/* CCM bitfields */
-#define CCM_PLL_MFI_SHIFT	10
-#define CCM_PLL_MFI_MASK	0xf
-#define CCM_PLL_MFN_SHIFT	0
-#define CCM_PLL_MFN_MASK	0x3ff
-#define CCM_PLL_MFD_SHIFT	16
-#define CCM_PLL_MFD_MASK	0x3ff
-#define CCM_PLL_PD_SHIFT	26
-#define CCM_PLL_PD_MASK		0xf
-#define CCM_CCTL_ARM_DIV_SHIFT	30
-#define CCM_CCTL_ARM_DIV_MASK	3
-#define CCM_CCTL_AHB_DIV_SHIFT	28
-#define CCM_CCTL_AHB_DIV_MASK	3
-#define CCM_CCTL_ARM_SRC	(1 << 14)
-#define CCM_CGR1_GPT1		(1 << 19)
-#define CCM_PERCLK_REG(clk)	(clk / 4)
-#define CCM_PERCLK_SHIFT(clk)	(8 * (clk % 4))
-#define CCM_PERCLK_MASK		0x3f
-#define CCM_RCSR_NF_16BIT_SEL	(1 << 14)
-#define CCM_RCSR_NF_PS(v)	((v >> 26) & 3)
-#define CCM_CRDR_BT_UART_SRC_SHIFT	29
-#define CCM_CRDR_BT_UART_SRC_MASK	7
-
-/* ESDRAM Controller register bitfields */
-#define ESDCTL_PRCT(x)		(((x) & 0x3f) << 0)
-#define ESDCTL_BL		(1 << 7)
-#define ESDCTL_FP		(1 << 8)
-#define ESDCTL_PWDT(x)		(((x) & 3) << 10)
-#define ESDCTL_SREFR(x)		(((x) & 7) << 13)
-#define ESDCTL_DSIZ_16_UPPER	(0 << 16)
-#define ESDCTL_DSIZ_16_LOWER	(1 << 16)
-#define ESDCTL_DSIZ_32		(2 << 16)
-#define ESDCTL_COL8		(0 << 20)
-#define ESDCTL_COL9		(1 << 20)
-#define ESDCTL_COL10		(2 << 20)
-#define ESDCTL_ROW11		(0 << 24)
-#define ESDCTL_ROW12		(1 << 24)
-#define ESDCTL_ROW13		(2 << 24)
-#define ESDCTL_ROW14		(3 << 24)
-#define ESDCTL_ROW15		(4 << 24)
-#define ESDCTL_SP		(1 << 27)
-#define ESDCTL_SMODE_NORMAL	(0 << 28)
-#define ESDCTL_SMODE_PRECHARGE	(1 << 28)
-#define ESDCTL_SMODE_AUTO_REF	(2 << 28)
-#define ESDCTL_SMODE_LOAD_MODE	(3 << 28)
-#define ESDCTL_SMODE_MAN_REF	(4 << 28)
-#define ESDCTL_SDE		(1 << 31)
-
-#define ESDCFG_TRC(x)		(((x) & 0xf) << 0)
-#define ESDCFG_TRCD(x)		(((x) & 0x7) << 4)
-#define ESDCFG_TCAS(x)		(((x) & 0x3) << 8)
-#define ESDCFG_TRRD(x)		(((x) & 0x3) << 10)
-#define ESDCFG_TRAS(x)		(((x) & 0x7) << 12)
-#define ESDCFG_TWR		(1 << 15)
-#define ESDCFG_TMRD(x)		(((x) & 0x3) << 16)
-#define ESDCFG_TRP(x)		(((x) & 0x3) << 18)
-#define ESDCFG_TWTR		(1 << 20)
-#define ESDCFG_TXP(x)		(((x) & 0x3) << 21)
-
-#define ESDMISC_RST		(1 << 1)
-#define ESDMISC_MDDREN		(1 << 2)
-#define ESDMISC_MDDR_DL_RST	(1 << 3)
-#define ESDMISC_MDDR_MDIS	(1 << 4)
-#define ESDMISC_LHD		(1 << 5)
-#define ESDMISC_MA10_SHARE	(1 << 6)
-#define ESDMISC_SDRAM_RDY	(1 << 31)
-
-/* GPT bits */
-#define GPT_CTRL_SWR		(1 << 15)	/* Software reset */
-#define GPT_CTRL_FRR		(1 << 9)	/* Freerun / restart */
-#define GPT_CTRL_CLKSOURCE_32	(4 << 6)	/* Clock source	*/
-#define GPT_CTRL_TEN		1		/* Timer enable	*/
-
-/* WDOG enable */
-#define WCR_WDE			0x04
-#define WSR_UNLOCK1		0x5555
-#define WSR_UNLOCK2		0xAAAA
-
-/* MAX bits */
-#define MAX_MGPCR_AULB(x)	(((x) & 0x7) << 0)
-
-/* M3IF bits */
-#define M3IF_CTL_MRRP(x)	(((x) & 0xff) << 0)
-
-/* WEIM bits */
-/* 13 fields of the upper CS control register */
-#define WEIM_CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
-		cnc, wsc, ew, wws, edc) \
-		((sp) << 31 | (wp) << 30 | (bcd) << 28 | (bcs) << 24 | \
-		(psz) << 22 | (pme) << 21 | (sync) << 20 | (dol) << 16 | \
-		(cnc) << 14 | (wsc) << 8 | (ew) << 7 | (wws) << 4 | (edc) << 0)
-/* 12 fields of the lower CS control register */
-#define WEIM_CSCR_L(oea, oen, ebwa, ebwn, \
-		csa, ebc, dsz, csn, psr, cre, wrap, csen) \
-		((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\
-		(csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\
-		(psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0)
-/* 14 fields of the additional CS control register */
-#define WEIM_CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \
-		wwu, age, cnc2, fce) \
-		((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\
-		(mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\
-		(dww) << 6 | (dct) << 4 | (wwu) << 3 |\
-		(age) << 2 | (cnc2) << 1 | (fce) << 0)
-
-/* Names used in GPIO driver */
-#define GPIO1_BASE_ADDR		IMX_GPIO1_BASE
-#define GPIO2_BASE_ADDR		IMX_GPIO2_BASE
-#define GPIO3_BASE_ADDR		IMX_GPIO3_BASE
-#define GPIO4_BASE_ADDR		IMX_GPIO4_BASE
-
-/*
- * CSPI register definitions
- */
-#define MXC_SPI_BASE_ADDRESSES \
-	IMX_CSPI1_BASE, \
-	IMX_CSPI2_BASE, \
-	IMX_CSPI3_BASE
-
-#endif				/* _IMX_REGS_H */

+ 0 - 537
arch/arm/include/asm/arch-mx25/iomux-mx25.h

@@ -1,537 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013 ADVANSEE
- * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
- *
- * Based on mainline Linux i.MX iomux-mx25.h file:
- * Copyright (C) 2009 by Lothar Wassmann <LW@KARO-electronics.de>
- *
- * Based on Linux arch/arm/mach-mx25/mx25_pins.h:
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * and Linux arch/arm/plat-mxc/include/mach/iomux-mx35.h:
- * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
- */
-
-#ifndef __IOMUX_MX25_H__
-#define __IOMUX_MX25_H__
-
-#include <asm/mach-imx/iomux-v3.h>
-
-/* Pad control groupings */
-#define MX25_KPP_ROW_PAD_CTRL	PAD_CTL_PUS_100K_UP
-#define MX25_KPP_COL_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
-
-/*
- * The naming convention for the pad modes is MX25_PAD_<padname>__<padmode>
- * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
- * See also iomux-v3.h
- */
-
-/*							    PAD    MUX    ALT INPSE PATH PADCTRL */
-enum {
-	MX25_PAD_A10__A10			= IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A10__GPIO_4_0			= IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_A13__A13			= IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A13__GPIO_4_1			= IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_A14__A14			= IOMUX_PAD(0x230, 0x010, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A14__GPIO_2_0			= IOMUX_PAD(0x230, 0x010, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_A15__A15			= IOMUX_PAD(0x234, 0x014, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A15__GPIO_2_1			= IOMUX_PAD(0x234, 0x014, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_A16__A16			= IOMUX_PAD(0x000, 0x018, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A16__GPIO_2_2			= IOMUX_PAD(0x000, 0x018, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_A17__A17			= IOMUX_PAD(0x238, 0x01c, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A17__GPIO_2_3			= IOMUX_PAD(0x238, 0x01c, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_A18__A18			= IOMUX_PAD(0x23c, 0x020, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A18__GPIO_2_4			= IOMUX_PAD(0x23c, 0x020, 0x05, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A18__FEC_COL			= IOMUX_PAD(0x23c, 0x020, 0x07, 0x504, 0, NO_PAD_CTRL),
-
-	MX25_PAD_A19__A19			= IOMUX_PAD(0x240, 0x024, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A19__FEC_RX_ER			= IOMUX_PAD(0x240, 0x024, 0x07, 0x518, 0, NO_PAD_CTRL),
-	MX25_PAD_A19__GPIO_2_5			= IOMUX_PAD(0x240, 0x024, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_A20__A20			= IOMUX_PAD(0x244, 0x028, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A20__GPIO_2_6			= IOMUX_PAD(0x244, 0x028, 0x05, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A20__FEC_RDATA2		= IOMUX_PAD(0x244, 0x028, 0x07, 0x50c, 0, NO_PAD_CTRL),
-
-	MX25_PAD_A21__A21			= IOMUX_PAD(0x248, 0x02c, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A21__GPIO_2_7			= IOMUX_PAD(0x248, 0x02c, 0x05, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A21__FEC_RDATA3		= IOMUX_PAD(0x248, 0x02c, 0x07, 0x510, 0, NO_PAD_CTRL),
-
-	MX25_PAD_A22__A22			= IOMUX_PAD(0x000, 0x030, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A22__GPIO_2_8			= IOMUX_PAD(0x000, 0x030, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_A23__A23			= IOMUX_PAD(0x24c, 0x034, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A23__GPIO_2_9			= IOMUX_PAD(0x24c, 0x034, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_A24__A24			= IOMUX_PAD(0x250, 0x038, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A24__GPIO_2_10			= IOMUX_PAD(0x250, 0x038, 0x05, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A24__FEC_RX_CLK		= IOMUX_PAD(0x250, 0x038, 0x07, 0x514, 0, NO_PAD_CTRL),
-
-	MX25_PAD_A25__A25			= IOMUX_PAD(0x254, 0x03c, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A25__GPIO_2_11			= IOMUX_PAD(0x254, 0x03c, 0x05, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_A25__FEC_CRS			= IOMUX_PAD(0x254, 0x03c, 0x07, 0x508, 0, NO_PAD_CTRL),
-
-	MX25_PAD_EB0__EB0			= IOMUX_PAD(0x258, 0x040, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_EB0__AUD4_TXD			= IOMUX_PAD(0x258, 0x040, 0x04, 0x464, 0, NO_PAD_CTRL),
-	MX25_PAD_EB0__GPIO_2_12			= IOMUX_PAD(0x258, 0x040, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_EB1__EB1			= IOMUX_PAD(0x25c, 0x044, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_EB1__AUD4_RXD			= IOMUX_PAD(0x25c, 0x044, 0x04, 0x460, 0, NO_PAD_CTRL),
-	MX25_PAD_EB1__GPIO_2_13			= IOMUX_PAD(0x25c, 0x044, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_OE__OE				= IOMUX_PAD(0x260, 0x048, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_OE__AUD4_TXC			= IOMUX_PAD(0x260, 0x048, 0x04, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_OE__GPIO_2_14			= IOMUX_PAD(0x260, 0x048, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_CS0__CS0			= IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CS0__GPIO_4_2			= IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_CS1__CS1			= IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CS1__NF_CE3			= IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CS1__GPIO_4_3			= IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_CS4__CS4			= IOMUX_PAD(0x264, 0x054, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CS4__NF_CE1			= IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CS4__UART5_CTS			= IOMUX_PAD(0x264, 0x054, 0x03, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CS4__GPIO_3_20			= IOMUX_PAD(0x264, 0x054, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_CS5__CS5			= IOMUX_PAD(0x268, 0x058, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CS5__NF_CE2			= IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CS5__UART5_RTS			= IOMUX_PAD(0x268, 0x058, 0x03, 0x574, 0, NO_PAD_CTRL),
-	MX25_PAD_CS5__GPIO_3_21			= IOMUX_PAD(0x268, 0x058, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_NF_CE0__NF_CE0			= IOMUX_PAD(0x26c, 0x05c, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_NF_CE0__GPIO_3_22		= IOMUX_PAD(0x26c, 0x05c, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_ECB__ECB			= IOMUX_PAD(0x270, 0x060, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_ECB__UART5_TXD_MUX		= IOMUX_PAD(0x270, 0x060, 0x03, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_ECB__GPIO_3_23			= IOMUX_PAD(0x270, 0x060, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_LBA__LBA			= IOMUX_PAD(0x274, 0x064, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_LBA__UART5_RXD_MUX		= IOMUX_PAD(0x274, 0x064, 0x03, 0x578, 0, NO_PAD_CTRL),
-	MX25_PAD_LBA__GPIO_3_24			= IOMUX_PAD(0x274, 0x064, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_BCLK__BCLK			= IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_BCLK__GPIO_4_4			= IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_RW__RW				= IOMUX_PAD(0x278, 0x06c, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_RW__AUD4_TXFS			= IOMUX_PAD(0x278, 0x06c, 0x04, 0x474, 0, NO_PAD_CTRL),
-	MX25_PAD_RW__GPIO_3_25			= IOMUX_PAD(0x278, 0x06c, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_NFWE_B__NFWE_B			= IOMUX_PAD(0x000, 0x070, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_NFWE_B__GPIO_3_26		= IOMUX_PAD(0x000, 0x070, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_NFRE_B__NFRE_B			= IOMUX_PAD(0x000, 0x074, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_NFRE_B__GPIO_3_27		= IOMUX_PAD(0x000, 0x074, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_NFALE__NFALE			= IOMUX_PAD(0x000, 0x078, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_NFALE__GPIO_3_28		= IOMUX_PAD(0x000, 0x078, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_NFCLE__NFCLE			= IOMUX_PAD(0x000, 0x07c, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_NFCLE__GPIO_3_29		= IOMUX_PAD(0x000, 0x07c, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_NFWP_B__NFWP_B			= IOMUX_PAD(0x000, 0x080, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_NFWP_B__GPIO_3_30		= IOMUX_PAD(0x000, 0x080, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_NFRB__NFRB			= IOMUX_PAD(0x27c, 0x084, 0x00, 0, 0, PAD_CTL_PKE),
-	MX25_PAD_NFRB__GPIO_3_31		= IOMUX_PAD(0x27c, 0x084, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_D15__D15			= IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_D15__LD16			= IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_D15__GPIO_4_5			= IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_D14__D14			= IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_D14__LD17			= IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_D14__GPIO_4_6			= IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_D13__D13			= IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_D13__LD18			= IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_D13__GPIO_4_7			= IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_D12__D12			= IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_D12__GPIO_4_8			= IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_D11__D11			= IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_D11__GPIO_4_9			= IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_D10__D10			= IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_D10__GPIO_4_10			= IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_D10__USBOTG_OC			= IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP),
-
-	MX25_PAD_D9__D9				= IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_D9__GPIO_4_11			= IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_D9__USBH2_PWR			= IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE),
-
-	MX25_PAD_D8__D8				= IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_D8__GPIO_4_12			= IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_D8__USBH2_OC			= IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP),
-
-	MX25_PAD_D7__D7				= IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_D7__GPIO_4_13			= IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_D6__D6				= IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_D6__GPIO_4_14			= IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_D5__D5				= IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_D5__GPIO_4_15			= IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_D4__D4				= IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_D4__GPIO_4_16			= IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_D3__D3				= IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_D3__GPIO_4_17			= IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_D2__D2				= IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_D2__GPIO_4_18			= IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_D1__D1				= IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_D1__GPIO_4_19			= IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_D0__D0				= IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_D0__GPIO_4_20			= IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_LD0__LD0			= IOMUX_PAD(0x2c0, 0x0c8, 0x00, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD0__CSI_D0			= IOMUX_PAD(0x2c0, 0x0c8, 0x02, 0x488, 0, NO_PAD_CTRL),
-	MX25_PAD_LD0__GPIO_2_15			= IOMUX_PAD(0x2c0, 0x0c8, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_LD1__LD1			= IOMUX_PAD(0x2c4, 0x0cc, 0x00, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD1__CSI_D1			= IOMUX_PAD(0x2c4, 0x0cc, 0x02, 0x48c, 0, NO_PAD_CTRL),
-	MX25_PAD_LD1__GPIO_2_16			= IOMUX_PAD(0x2c4, 0x0cc, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_LD2__LD2			= IOMUX_PAD(0x2c8, 0x0d0, 0x00, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD2__GPIO_2_17			= IOMUX_PAD(0x2c8, 0x0d0, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_LD3__LD3			= IOMUX_PAD(0x2cc, 0x0d4, 0x00, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD3__GPIO_2_18			= IOMUX_PAD(0x2cc, 0x0d4, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_LD4__LD4			= IOMUX_PAD(0x2d0, 0x0d8, 0x00, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD4__GPIO_2_19			= IOMUX_PAD(0x2d0, 0x0d8, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_LD5__LD5			= IOMUX_PAD(0x2d4, 0x0dc, 0x00, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD5__GPIO_1_19			= IOMUX_PAD(0x2d4, 0x0dc, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_LD6__LD6			= IOMUX_PAD(0x2d8, 0x0e0, 0x00, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD6__GPIO_1_20			= IOMUX_PAD(0x2d8, 0x0e0, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_LD7__LD7			= IOMUX_PAD(0x2dc, 0x0e4, 0x00, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD7__GPIO_1_21			= IOMUX_PAD(0x2dc, 0x0e4, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_LD8__LD8			= IOMUX_PAD(0x2e0, 0x0e8, 0x00, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD8__FEC_TX_ERR		= IOMUX_PAD(0x2e0, 0x0e8, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_LD9__LD9			= IOMUX_PAD(0x2e4, 0x0ec, 0x00, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD9__FEC_COL			= IOMUX_PAD(0x2e4, 0x0ec, 0x05, 0x504, 1, NO_PAD_CTRL),
-
-	MX25_PAD_LD10__LD10			= IOMUX_PAD(0x2e8, 0x0f0, 0x00, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD10__FEC_RX_ER		= IOMUX_PAD(0x2e8, 0x0f0, 0x05, 0x518, 1, NO_PAD_CTRL),
-
-	MX25_PAD_LD11__LD11			= IOMUX_PAD(0x2ec, 0x0f4, 0x00, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD11__FEC_RDATA2		= IOMUX_PAD(0x2ec, 0x0f4, 0x05, 0x50c, 1, NO_PAD_CTRL),
-
-	MX25_PAD_LD12__LD12			= IOMUX_PAD(0x2f0, 0x0f8, 0x00, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD12__FEC_RDATA3		= IOMUX_PAD(0x2f0, 0x0f8, 0x05, 0x510, 1, NO_PAD_CTRL),
-
-	MX25_PAD_LD13__LD13			= IOMUX_PAD(0x2f4, 0x0fc, 0x00, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD13__FEC_TDATA2		= IOMUX_PAD(0x2f4, 0x0fc, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_LD14__LD14			= IOMUX_PAD(0x2f8, 0x100, 0x00, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD14__FEC_TDATA3		= IOMUX_PAD(0x2f8, 0x100, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_LD15__LD15			= IOMUX_PAD(0x2fc, 0x104, 0x00, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_LD15__FEC_RX_CLK		= IOMUX_PAD(0x2fc, 0x104, 0x05, 0x514, 1, NO_PAD_CTRL),
-
-	MX25_PAD_HSYNC__HSYNC			= IOMUX_PAD(0x300, 0x108, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_HSYNC__GPIO_1_22		= IOMUX_PAD(0x300, 0x108, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_VSYNC__VSYNC			= IOMUX_PAD(0x304, 0x10c, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_VSYNC__GPIO_1_23		= IOMUX_PAD(0x304, 0x10c, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_LSCLK__LSCLK			= IOMUX_PAD(0x308, 0x110, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_LSCLK__GPIO_1_24		= IOMUX_PAD(0x308, 0x110, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_OE_ACD__OE_ACD			= IOMUX_PAD(0x30c, 0x114, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_OE_ACD__GPIO_1_25		= IOMUX_PAD(0x30c, 0x114, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_CONTRAST__CONTRAST		= IOMUX_PAD(0x310, 0x118, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CONTRAST__PWM4_PWMO		= IOMUX_PAD(0x310, 0x118, 0x04, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CONTRAST__FEC_CRS		= IOMUX_PAD(0x310, 0x118, 0x05, 0x508, 1, NO_PAD_CTRL),
-
-	MX25_PAD_PWM__PWM			= IOMUX_PAD(0x314, 0x11c, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_PWM__GPIO_1_26			= IOMUX_PAD(0x314, 0x11c, 0x05, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_PWM__USBH2_OC			= IOMUX_PAD(0x314, 0x11c, 0x06, 0x580, 1, PAD_CTL_PUS_100K_UP),
-
-	MX25_PAD_CSI_D2__CSI_D2			= IOMUX_PAD(0x318, 0x120, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_D2__UART5_RXD_MUX		= IOMUX_PAD(0x318, 0x120, 0x01, 0x578, 1, NO_PAD_CTRL),
-	MX25_PAD_CSI_D2__GPIO_1_27		= IOMUX_PAD(0x318, 0x120, 0x05, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_D2__CSPI3_MOSI		= IOMUX_PAD(0x318, 0x120, 0x07, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_CSI_D3__CSI_D3			= IOMUX_PAD(0x31c, 0x124, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_D3__GPIO_1_28		= IOMUX_PAD(0x31c, 0x124, 0x05, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_D3__CSPI3_MISO		= IOMUX_PAD(0x31c, 0x124, 0x07, 0x4b4, 1, NO_PAD_CTRL),
-
-	MX25_PAD_CSI_D4__CSI_D4			= IOMUX_PAD(0x320, 0x128, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_D4__UART5_RTS		= IOMUX_PAD(0x320, 0x128, 0x01, 0x574, 1, NO_PAD_CTRL),
-	MX25_PAD_CSI_D4__GPIO_1_29		= IOMUX_PAD(0x320, 0x128, 0x05, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_D4__CSPI3_SCLK		= IOMUX_PAD(0x320, 0x128, 0x07, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_CSI_D5__CSI_D5			= IOMUX_PAD(0x324, 0x12c, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_D5__GPIO_1_30		= IOMUX_PAD(0x324, 0x12c, 0x05, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_D5__CSPI3_RDY		= IOMUX_PAD(0x324, 0x12c, 0x07, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_CSI_D6__CSI_D6			= IOMUX_PAD(0x328, 0x130, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_D6__GPIO_1_31		= IOMUX_PAD(0x328, 0x130, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_CSI_D7__CSI_D7			= IOMUX_PAD(0x32c, 0x134, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_D7__GPIO_1_6		= IOMUX_PAD(0x32c, 0x134, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_CSI_D8__CSI_D8			= IOMUX_PAD(0x330, 0x138, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_D8__GPIO_1_7		= IOMUX_PAD(0x330, 0x138, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_CSI_D9__CSI_D9			= IOMUX_PAD(0x334, 0x13c, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_D9__GPIO_4_21		= IOMUX_PAD(0x334, 0x13c, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_CSI_MCLK__CSI_MCLK		= IOMUX_PAD(0x338, 0x140, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_MCLK__GPIO_1_8		= IOMUX_PAD(0x338, 0x140, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_CSI_VSYNC__CSI_VSYNC		= IOMUX_PAD(0x33c, 0x144, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_VSYNC__GPIO_1_9		= IOMUX_PAD(0x33c, 0x144, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_CSI_HSYNC__CSI_HSYNC		= IOMUX_PAD(0x340, 0x148, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_HSYNC__GPIO_1_10		= IOMUX_PAD(0x340, 0x148, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_CSI_PIXCLK__CSI_PIXCLK		= IOMUX_PAD(0x344, 0x14c, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSI_PIXCLK__GPIO_1_11		= IOMUX_PAD(0x344, 0x14c, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_I2C1_CLK__I2C1_CLK		= IOMUX_PAD(0x348, 0x150, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_I2C1_CLK__GPIO_1_12		= IOMUX_PAD(0x348, 0x150, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_I2C1_DAT__I2C1_DAT		= IOMUX_PAD(0x34c, 0x154, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_I2C1_DAT__GPIO_1_13		= IOMUX_PAD(0x34c, 0x154, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_CSPI1_MOSI__CSPI1_MOSI		= IOMUX_PAD(0x350, 0x158, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSPI1_MOSI__GPIO_1_14		= IOMUX_PAD(0x350, 0x158, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_CSPI1_MISO__CSPI1_MISO		= IOMUX_PAD(0x354, 0x15c, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSPI1_MISO__GPIO_1_15		= IOMUX_PAD(0x354, 0x15c, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_CSPI1_SS0__CSPI1_SS0		= IOMUX_PAD(0x358, 0x160, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSPI1_SS0__GPIO_1_16		= IOMUX_PAD(0x358, 0x160, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_CSPI1_SS1__CSPI1_SS1		= IOMUX_PAD(0x35c, 0x164, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSPI1_SS1__I2C3_DAT		= IOMUX_PAD(0x35c, 0x164, 0x01, 0x528, 1, NO_PAD_CTRL),
-	MX25_PAD_CSPI1_SS1__GPIO_1_17		= IOMUX_PAD(0x35c, 0x164, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_CSPI1_SCLK__CSPI1_SCLK		= IOMUX_PAD(0x360, 0x168, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CSPI1_SCLK__GPIO_1_18		= IOMUX_PAD(0x360, 0x168, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_CSPI1_RDY__CSPI1_RDY		= IOMUX_PAD(0x364, 0x16c, 0x00, 0, 0, PAD_CTL_PKE),
-	MX25_PAD_CSPI1_RDY__GPIO_2_22		= IOMUX_PAD(0x364, 0x16c, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_UART1_RXD__UART1_RXD		= IOMUX_PAD(0x368, 0x170, 0x00, 0, 0, PAD_CTL_PUS_100K_DOWN),
-	MX25_PAD_UART1_RXD__GPIO_4_22		= IOMUX_PAD(0x368, 0x170, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_UART1_TXD__UART1_TXD		= IOMUX_PAD(0x36c, 0x174, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_UART1_TXD__GPIO_4_23		= IOMUX_PAD(0x36c, 0x174, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_UART1_RTS__UART1_RTS		= IOMUX_PAD(0x370, 0x178, 0x00, 0, 0, PAD_CTL_PUS_100K_UP),
-	MX25_PAD_UART1_RTS__CSI_D0		= IOMUX_PAD(0x370, 0x178, 0x01, 0x488, 1, NO_PAD_CTRL),
-	MX25_PAD_UART1_RTS__GPIO_4_24		= IOMUX_PAD(0x370, 0x178, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_UART1_CTS__UART1_CTS		= IOMUX_PAD(0x374, 0x17c, 0x00, 0, 0, PAD_CTL_PUS_100K_UP),
-	MX25_PAD_UART1_CTS__CSI_D1		= IOMUX_PAD(0x374, 0x17c, 0x01, 0x48c, 1, NO_PAD_CTRL),
-	MX25_PAD_UART1_CTS__GPIO_4_25		= IOMUX_PAD(0x374, 0x17c, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_UART2_RXD__UART2_RXD		= IOMUX_PAD(0x378, 0x180, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_UART2_RXD__GPIO_4_26		= IOMUX_PAD(0x378, 0x180, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_UART2_TXD__UART2_TXD		= IOMUX_PAD(0x37c, 0x184, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_UART2_TXD__GPIO_4_27		= IOMUX_PAD(0x37c, 0x184, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_UART2_RTS__UART2_RTS		= IOMUX_PAD(0x380, 0x188, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_UART2_RTS__FEC_COL		= IOMUX_PAD(0x380, 0x188, 0x02, 0x504, 2, NO_PAD_CTRL),
-	MX25_PAD_UART2_RTS__GPIO_4_28		= IOMUX_PAD(0x380, 0x188, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_UART2_CTS__FEC_RX_ER		= IOMUX_PAD(0x384, 0x18c, 0x02, 0x518, 2, NO_PAD_CTRL),
-	MX25_PAD_UART2_CTS__UART2_CTS		= IOMUX_PAD(0x384, 0x18c, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_UART2_CTS__GPIO_4_29		= IOMUX_PAD(0x384, 0x18c, 0x05, 0, 0, NO_PAD_CTRL),
-
-	/*
-	 * Removing the SION bit from MX25_PAD_SD1_CMD__SD1_CMD breaks detecting an SD
-	 * card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM
-	 * Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon
-	 * bug that configuring the SD1_CMD function doesn't enable the input path for
-	 * this pin.
-	 * This might have side effects for other hardware units that are connected to
-	 * that pin and use the respective function as input.
-	 */
-	MX25_PAD_SD1_CMD__SD1_CMD		= IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
-	MX25_PAD_SD1_CMD__FEC_RDATA2		= IOMUX_PAD(0x388, 0x190, 0x02, 0x50c, 2, NO_PAD_CTRL),
-	MX25_PAD_SD1_CMD__GPIO_2_23		= IOMUX_PAD(0x388, 0x190, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_SD1_CLK__SD1_CLK		= IOMUX_PAD(0x38c, 0x194, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
-	MX25_PAD_SD1_CLK__FEC_RDATA3		= IOMUX_PAD(0x38c, 0x194, 0x02, 0x510, 2, NO_PAD_CTRL),
-	MX25_PAD_SD1_CLK__GPIO_2_24		= IOMUX_PAD(0x38c, 0x194, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_SD1_DATA0__SD1_DATA0		= IOMUX_PAD(0x390, 0x198, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
-	MX25_PAD_SD1_DATA0__GPIO_2_25		= IOMUX_PAD(0x390, 0x198, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_SD1_DATA1__SD1_DATA1		= IOMUX_PAD(0x394, 0x19c, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
-	MX25_PAD_SD1_DATA1__AUD7_RXD		= IOMUX_PAD(0x394, 0x19c, 0x03, 0x478, 0, NO_PAD_CTRL),
-	MX25_PAD_SD1_DATA1__GPIO_2_26		= IOMUX_PAD(0x394, 0x19c, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_SD1_DATA2__SD1_DATA2		= IOMUX_PAD(0x398, 0x1a0, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
-	MX25_PAD_SD1_DATA2__FEC_RX_CLK		= IOMUX_PAD(0x398, 0x1a0, 0x05, 0x514, 2, NO_PAD_CTRL),
-	MX25_PAD_SD1_DATA2__GPIO_2_27		= IOMUX_PAD(0x398, 0x1a0, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_SD1_DATA3__SD1_DATA3		= IOMUX_PAD(0x39c, 0x1a4, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
-	MX25_PAD_SD1_DATA3__FEC_CRS		= IOMUX_PAD(0x39c, 0x1a4, 0x00, 0x508, 2, NO_PAD_CTRL),
-	MX25_PAD_SD1_DATA3__GPIO_2_28		= IOMUX_PAD(0x39c, 0x1a4, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_KPP_ROW0__KPP_ROW0		= IOMUX_PAD(0x3a0, 0x1a8, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL),
-	MX25_PAD_KPP_ROW0__GPIO_2_29		= IOMUX_PAD(0x3a0, 0x1a8, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_KPP_ROW1__KPP_ROW1		= IOMUX_PAD(0x3a4, 0x1ac, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL),
-	MX25_PAD_KPP_ROW1__GPIO_2_30		= IOMUX_PAD(0x3a4, 0x1ac, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_KPP_ROW2__KPP_ROW2		= IOMUX_PAD(0x3a8, 0x1b0, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL),
-	MX25_PAD_KPP_ROW2__CSI_D0		= IOMUX_PAD(0x3a8, 0x1b0, 0x03, 0x488, 2, NO_PAD_CTRL),
-	MX25_PAD_KPP_ROW2__GPIO_2_31		= IOMUX_PAD(0x3a8, 0x1b0, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_KPP_ROW3__KPP_ROW3		= IOMUX_PAD(0x3ac, 0x1b4, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL),
-	MX25_PAD_KPP_ROW3__CSI_LD1		= IOMUX_PAD(0x3ac, 0x1b4, 0x03, 0x48c, 2, NO_PAD_CTRL),
-	MX25_PAD_KPP_ROW3__GPIO_3_0		= IOMUX_PAD(0x3ac, 0x1b4, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_KPP_COL0__KPP_COL0		= IOMUX_PAD(0x3b0, 0x1b8, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL),
-	MX25_PAD_KPP_COL0__UART4_RXD_MUX	= IOMUX_PAD(0x3b0, 0x1b8, 0x01, 0x570, 1, NO_PAD_CTRL),
-	MX25_PAD_KPP_COL0__AUD5_TXD		= IOMUX_PAD(0x3b0, 0x1b8, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
-	MX25_PAD_KPP_COL0__GPIO_3_1		= IOMUX_PAD(0x3b0, 0x1b8, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_KPP_COL1__KPP_COL1		= IOMUX_PAD(0x3b4, 0x1bc, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL),
-	MX25_PAD_KPP_COL1__UART4_TXD_MUX	= IOMUX_PAD(0x3b4, 0x1bc, 0x01, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_KPP_COL1__AUD5_RXD		= IOMUX_PAD(0x3b4, 0x1bc, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
-	MX25_PAD_KPP_COL1__GPIO_3_2		= IOMUX_PAD(0x3b4, 0x1bc, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_KPP_COL2__KPP_COL2		= IOMUX_PAD(0x3b8, 0x1c0, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL),
-	MX25_PAD_KPP_COL2__UART4_RTS		= IOMUX_PAD(0x3b8, 0x1c0, 0x01, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_KPP_COL2__AUD5_TXC		= IOMUX_PAD(0x3b8, 0x1c0, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
-	MX25_PAD_KPP_COL2__GPIO_3_3		= IOMUX_PAD(0x3b8, 0x1c0, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_KPP_COL3__KPP_COL3		= IOMUX_PAD(0x3bc, 0x1c4, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL),
-	MX25_PAD_KPP_COL3__UART4_CTS		= IOMUX_PAD(0x3bc, 0x1c4, 0x01, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_KPP_COL3__AUD5_TXFS		= IOMUX_PAD(0x3bc, 0x1c4, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
-	MX25_PAD_KPP_COL3__GPIO_3_4		= IOMUX_PAD(0x3bc, 0x1c4, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_FEC_MDC__FEC_MDC		= IOMUX_PAD(0x3c0, 0x1c8, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_FEC_MDC__AUD4_TXD		= IOMUX_PAD(0x3c0, 0x1c8, 0x02, 0x464, 1, NO_PAD_CTRL),
-	MX25_PAD_FEC_MDC__GPIO_3_5		= IOMUX_PAD(0x3c0, 0x1c8, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_FEC_MDIO__FEC_MDIO		= IOMUX_PAD(0x3c4, 0x1cc, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
-	MX25_PAD_FEC_MDIO__AUD4_RXD		= IOMUX_PAD(0x3c4, 0x1cc, 0x02, 0x460, 1, NO_PAD_CTRL),
-	MX25_PAD_FEC_MDIO__GPIO_3_6		= IOMUX_PAD(0x3c4, 0x1cc, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_FEC_TDATA0__FEC_TDATA0		= IOMUX_PAD(0x3c8, 0x1d0, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_FEC_TDATA0__GPIO_3_7		= IOMUX_PAD(0x3c8, 0x1d0, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_FEC_TDATA1__FEC_TDATA1		= IOMUX_PAD(0x3cc, 0x1d4, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_FEC_TDATA1__AUD4_TXFS		= IOMUX_PAD(0x3cc, 0x1d4, 0x02, 0x474, 1, NO_PAD_CTRL),
-	MX25_PAD_FEC_TDATA1__GPIO_3_8		= IOMUX_PAD(0x3cc, 0x1d4, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_FEC_TX_EN__FEC_TX_EN		= IOMUX_PAD(0x3d0, 0x1d8, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_FEC_TX_EN__GPIO_3_9		= IOMUX_PAD(0x3d0, 0x1d8, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_FEC_RDATA0__FEC_RDATA0		= IOMUX_PAD(0x3d4, 0x1dc, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
-	MX25_PAD_FEC_RDATA0__GPIO_3_10		= IOMUX_PAD(0x3d4, 0x1dc, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_FEC_RDATA1__FEC_RDATA1		= IOMUX_PAD(0x3d8, 0x1e0, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
-	MX25_PAD_FEC_RDATA1__GPIO_3_11		= IOMUX_PAD(0x3d8, 0x1e0, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_FEC_RX_DV__FEC_RX_DV		= IOMUX_PAD(0x3dc, 0x1e4, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
-	MX25_PAD_FEC_RX_DV__CAN2_RX		= IOMUX_PAD(0x3dc, 0x1e4, 0x04, 0x484, 0, PAD_CTL_PUS_22K_UP),
-	MX25_PAD_FEC_RX_DV__GPIO_3_12		= IOMUX_PAD(0x3dc, 0x1e4, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_FEC_TX_CLK__FEC_TX_CLK		= IOMUX_PAD(0x3e0, 0x1e8, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
-	MX25_PAD_FEC_TX_CLK__GPIO_3_13		= IOMUX_PAD(0x3e0, 0x1e8, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_RTCK__RTCK			= IOMUX_PAD(0x3e4, 0x1ec, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_RTCK__OWIRE			= IOMUX_PAD(0x3e4, 0x1ec, 0x01, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_RTCK__GPIO_3_14		= IOMUX_PAD(0x3e4, 0x1ec, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_DE_B__DE_B			= IOMUX_PAD(0x3ec, 0x1f0, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_DE_B__GPIO_2_20		= IOMUX_PAD(0x3ec, 0x1f0, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_TDO__TDO			= IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_GPIO_A__GPIO_A			= IOMUX_PAD(0x3f0, 0x1f4, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_GPIO_A__CAN1_TX		= IOMUX_PAD(0x3f0, 0x1f4, 0x06, 0, 0, PAD_CTL_PUS_22K_UP),
-	MX25_PAD_GPIO_A__USBOTG_PWR		= IOMUX_PAD(0x3f0, 0x1f4, 0x02, 0, 0, PAD_CTL_PKE),
-
-	MX25_PAD_GPIO_B__GPIO_B			= IOMUX_PAD(0x3f4, 0x1f8, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_GPIO_B__CAN1_RX		= IOMUX_PAD(0x3f4, 0x1f8, 0x06, 0x480, 1, PAD_CTL_PUS_22K_UP),
-	MX25_PAD_GPIO_B__USBOTG_OC		= IOMUX_PAD(0x3f4, 0x1f8, 0x02, 0x57c, 1, PAD_CTL_PUS_100K_UP),
-
-	MX25_PAD_GPIO_C__GPIO_C			= IOMUX_PAD(0x3f8, 0x1fc, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_GPIO_C__CAN2_TX		= IOMUX_PAD(0x3f8, 0x1fc, 0x06, 0, 0, PAD_CTL_PUS_22K_UP),
-
-	MX25_PAD_GPIO_D__GPIO_D			= IOMUX_PAD(0x3fc, 0x200, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_GPIO_E__LD16			= IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_GPIO_D__CAN2_RX		= IOMUX_PAD(0x3fc, 0x200, 0x06, 0x484, 1, PAD_CTL_PUS_22K_UP),
-
-	MX25_PAD_GPIO_E__GPIO_E			= IOMUX_PAD(0x400, 0x204, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_GPIO_F__LD17			= IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST),
-	MX25_PAD_GPIO_E__I2C3_CLK		= IOMUX_PAD(0x400, 0x204, 0x01, 0x524, 2, NO_PAD_CTRL),
-	MX25_PAD_GPIO_E__AUD7_TXD		= IOMUX_PAD(0x400, 0x204, 0x04, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_GPIO_F__GPIO_F			= IOMUX_PAD(0x404, 0x208, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_GPIO_F__AUD7_TXC		= IOMUX_PAD(0x404, 0x208, 0x04, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_EXT_ARMCLK__EXT_ARMCLK		= IOMUX_PAD(0x000, 0x20c, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_EXT_ARMCLK__GPIO_3_15		= IOMUX_PAD(0x000, 0x20c, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK	= IOMUX_PAD(0x000, 0x210, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_UPLL_BYPCLK__GPIO_3_16		= IOMUX_PAD(0x000, 0x210, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_VSTBY_REQ__VSTBY_REQ		= IOMUX_PAD(0x408, 0x214, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_VSTBY_REQ__AUD7_TXFS		= IOMUX_PAD(0x408, 0x214, 0x04, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_VSTBY_REQ__GPIO_3_17		= IOMUX_PAD(0x408, 0x214, 0x05, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_VSTBY_ACK__VSTBY_ACK		= IOMUX_PAD(0x40c, 0x218, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_VSTBY_ACK__GPIO_3_18		= IOMUX_PAD(0x40c, 0x218, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_POWER_FAIL__POWER_FAIL		= IOMUX_PAD(0x410, 0x21c, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_POWER_FAIL__AUD7_RXD		= IOMUX_PAD(0x410, 0x21c, 0x04, 0x478, 1, NO_PAD_CTRL),
-	MX25_PAD_POWER_FAIL__GPIO_3_19		= IOMUX_PAD(0x410, 0x21c, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_CLKO__CLKO			= IOMUX_PAD(0x414, 0x220, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CLKO__GPIO_2_21		= IOMUX_PAD(0x414, 0x220, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_BOOT_MODE0__BOOT_MODE0		= IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_BOOT_MODE0__GPIO_4_30		= IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_BOOT_MODE1__BOOT_MODE1		= IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_BOOT_MODE1__GPIO_4_31		= IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL),
-
-	MX25_PAD_CTL_GRP_DVS_MISC		= IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CTL_GRP_DSE_FEC		= IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CTL_GRP_DVS_JTAG		= IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CTL_GRP_DSE_NFC		= IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CTL_GRP_DSE_CSI		= IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CTL_GRP_DSE_WEIM		= IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CTL_GRP_DSE_DDR		= IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CTL_GRP_DVS_CRM		= IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CTL_GRP_DSE_KPP		= IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CTL_GRP_DSE_SDHC1		= IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CTL_GRP_DSE_LCD		= IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CTL_GRP_DSE_UART		= IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CTL_GRP_DVS_NFC		= IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CTL_GRP_DVS_CSI		= IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CTL_GRP_DSE_CSPI1		= IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CTL_GRP_DDRTYPE		= IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CTL_GRP_DVS_SDHC1		= IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL),
-	MX25_PAD_CTL_GRP_DVS_LCD		= IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL),
-};
-
-#endif /* __IOMUX_MX25_H__ */

+ 0 - 90
arch/arm/include/asm/arch-mx25/macro.h

@@ -1,90 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011
- * Matthias Weisser <weisserm@arcor.de>
- *
- * (C) Copyright 2009 DENX Software Engineering
- * Author: John Rigby <jrigby@gmail.com>
- *
- * Common asm macros for imx25
- */
-
-#ifndef __ASM_ARM_ARCH_MACRO_H__
-#define __ASM_ARM_ARCH_MACRO_H__
-#ifdef __ASSEMBLY__
-
-#include <asm/arch/imx-regs.h>
-#include <generated/asm-offsets.h>
-#include <asm/macro.h>
-
-/*
- * AIPS setup - Only setup MPROTx registers.
- * The PACR default values are good.
- *
- * Default argument values:
- *  - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to
- *    user-mode.
- */
-.macro init_aips mpr=0x77777777
-	ldr	r0, =IMX_AIPS1_BASE
-	ldr	r1, =\mpr
-	str	r1, [r0, #AIPS_MPR_0_7]
-	str	r1, [r0, #AIPS_MPR_8_15]
-	ldr	r2, =IMX_AIPS2_BASE
-	str	r1, [r2, #AIPS_MPR_0_7]
-	str	r1, [r2, #AIPS_MPR_8_15]
-.endm
-
-/*
- * MAX (Multi-Layer AHB Crossbar Switch) setup
- *
- * Default argument values:
- *  - MPR: priority is IAHB > DAHB > USBOTG > RTIC > eSDHC2/SDMA
- *  - SGPCR: always park on last master
- *  - MGPCR: restore default values
- */
-.macro init_max mpr=0x00043210, sgpcr=0x00000010, mgpcr=0x00000000
-	ldr	r0, =IMX_MAX_BASE
-	ldr	r1, =\mpr
-	str	r1, [r0, #MAX_MPR0]	/* for S0 */
-	str	r1, [r0, #MAX_MPR1]	/* for S1 */
-	str	r1, [r0, #MAX_MPR2]	/* for S2 */
-	str	r1, [r0, #MAX_MPR3]	/* for S3 */
-	str	r1, [r0, #MAX_MPR4]	/* for S4 */
-	ldr	r1, =\sgpcr
-	str	r1, [r0, #MAX_SGPCR0]	/* for S0 */
-	str	r1, [r0, #MAX_SGPCR1]	/* for S1 */
-	str	r1, [r0, #MAX_SGPCR2]	/* for S2 */
-	str	r1, [r0, #MAX_SGPCR3]	/* for S3 */
-	str	r1, [r0, #MAX_SGPCR4]	/* for S4 */
-	ldr	r1, =\mgpcr
-	str	r1, [r0, #MAX_MGPCR0]	/* for M0 */
-	str	r1, [r0, #MAX_MGPCR1]	/* for M1 */
-	str	r1, [r0, #MAX_MGPCR2]	/* for M2 */
-	str	r1, [r0, #MAX_MGPCR3]	/* for M3 */
-	str	r1, [r0, #MAX_MGPCR4]	/* for M4 */
-.endm
-
-/*
- * M3IF setup
- *
- * Default argument values:
- *  - CTL:
- * MRRP[0] = LCDC on priority list (1 << 0)			= 0x00000001
- * MRRP[1] = MAX1 not on priority list (0 << 1)			= 0x00000000
- * MRRP[2] = MAX0 not on priority list (0 << 2)			= 0x00000000
- * MRRP[3] = USBH not on priority list (0 << 3)			= 0x00000000
- * MRRP[4] = SDMA not on priority list (0 << 4)			= 0x00000000
- * MRRP[5] = eSDHC1/ATA/FEC not on priority list (0 << 5)	= 0x00000000
- * MRRP[6] = LCDC/SLCDC/MAX2 not on priority list (0 << 6)	= 0x00000000
- * MRRP[7] = CSI not on priority list (0 << 7)			= 0x00000000
- *								------------
- *								  0x00000001
- */
-.macro init_m3if ctl=0x00000001
-	/* M3IF Control Register (M3IFCTL) */
-	write32	IMX_M3IF_CTRL_BASE, \ctl
-.endm
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ASM_ARM_ARCH_MACRO_H__ */

+ 1 - 37
arch/arm/lib/asm-offsets.c

@@ -15,7 +15,7 @@
 #include <linux/kbuild.h>
 #include <linux/arm-smccc.h>
 
-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) \
+#if defined(CONFIG_MX27) \
 	|| defined(CONFIG_MX51) || defined(CONFIG_MX53)
 #include <asm/arch/imx-regs.h>
 #endif
@@ -35,42 +35,6 @@ int main(void)
 	 * code. Is it better to define the macros directly in headers?
 	 */
 
-#if defined(CONFIG_MX25)
-	/* Clock Control Module */
-	DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
-	DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0));
-	DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1));
-	DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2));
-	DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2]));
-	DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr));
-
-	/* Enhanced SDRAM Controller */
-	DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0));
-	DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0));
-	DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc));
-
-	/* Multi-Layer AHB Crossbar Switch */
-	DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
-	DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
-	DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
-	DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
-	DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
-	DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
-	DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
-	DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
-	DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
-	DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
-	DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
-	DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
-	DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
-	DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
-	DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
-
-	/* AHB <-> IP-Bus Interface */
-	DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
-	DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
-#endif
-
 #if defined(CONFIG_MX27)
 	DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
 	DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));

+ 0 - 23
arch/arm/mach-imx/mx2/Kconfig

@@ -1,23 +0,0 @@
-if ARCH_MX25
-
-config MX25
-	bool
-	default y
-	select SYS_FSL_ERRATUM_ESDHC_A001
-choice
-	prompt "MX25 board select"
-	optional
-
-config TARGET_ZMX25
-	bool "Support zmx25"
-	select BOARD_LATE_INIT
-	select CPU_ARM926EJS
-
-endchoice
-
-config SYS_SOC
-	default "mx25"
-
-source "board/syteco/zmx25/Kconfig"
-
-endif

+ 0 - 15
board/syteco/zmx25/Kconfig

@@ -1,15 +0,0 @@
-if TARGET_ZMX25
-
-config SYS_BOARD
-	default "zmx25"
-
-config SYS_VENDOR
-	default "syteco"
-
-config SYS_SOC
-	default "mx25"
-
-config SYS_CONFIG_NAME
-	default "zmx25"
-
-endif

+ 0 - 6
board/syteco/zmx25/MAINTAINERS

@@ -1,6 +0,0 @@
-ZMX25 BOARD
-M:	Matthias Weisser <weisserm@arcor.de>
-S:	Maintained
-F:	board/syteco/zmx25/
-F:	include/configs/zmx25.h
-F:	configs/zmx25_defconfig

+ 0 - 7
board/syteco/zmx25/Makefile

@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (c) 2010 Graf-Syteco, Matthias Weisser
-# <weisserm@arcor.de>
-
-obj-y	+= zmx25.o
-obj-y	+= lowlevel_init.o

+ 0 - 96
board/syteco/zmx25/lowlevel_init.S

@@ -1,96 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2011
- * Matthias Weisser <weisserm@arcor.de>
- *
- * (C) Copyright 2009 DENX Software Engineering
- * Author: John Rigby <jrigby@gmail.com>
- *
- * Based on U-Boot and RedBoot sources for several different i.mx
- * platforms.
- */
-
-#include <asm/macro.h>
-#include <asm/arch/macro.h>
-#include <asm/arch/imx-regs.h>
-#include <generated/asm-offsets.h>
-
-/*
- * clocks
- */
-.macro init_clocks
-
-	/* disable clock output */
-	write32	IMX_CCM_BASE + CCM_MCR, 0x00000000
-	write32	IMX_CCM_BASE + CCM_CCTL, 0x50030000
-
-	/*
-	 * enable all implemented clocks in all three
-	 * clock control registers
-	 */
-	write32	IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff
-	write32	IMX_CCM_BASE + CCM_CGCR1, 0xffffffff
-	write32	IMX_CCM_BASE + CCM_CGCR2, 0xfffff
-
-	/* Devide NAND clock by 32 */
-	write32	IMX_CCM_BASE + CCM_PCDR2, 0x0101011F
-.endm
-
-/*
- * sdram controller init
- */
-.macro init_lpddr
-	ldr	r0, =IMX_ESDRAMC_BASE
-	ldr	r2, =IMX_SDRAM_BANK0_BASE
-
-	/*
-	 * reset SDRAM controller
-	 * then wait for initialization to complete
-	 */
-	ldr	r1, =(1 << 1) | (1 << 2)
-	str	r1, [r0, #ESDRAMC_ESDMISC]
-1:	ldr	r3, [r0, #ESDRAMC_ESDMISC]
-	tst	r3, #(1 << 31)
-	beq	1b
-	ldr	r1, =(1 << 2)
-	str	r1, [r0, #ESDRAMC_ESDMISC]
-
-	ldr	r1, =0x002a7420
-	str	r1, [r0, #ESDRAMC_ESDCFG0]
-
-	/* control | precharge */
-	ldr	r1, =0x92216008
-	str	r1, [r0, #ESDRAMC_ESDCTL0]
-	/* dram command encoded in address */
-	str	r1, [r2, #0x400]
-
-	/* auto refresh */
-	ldr	r1, =0xa2216008
-	str	r1, [r0, #ESDRAMC_ESDCTL0]
-	/* read dram twice to auto refresh */
-	ldr	    r3, [r2]
-	ldr     r3, [r2]
-
-	/* control | load mode */
-	ldr	r1, =0xb2216008
-	str	r1, [r0, #ESDRAMC_ESDCTL0]
-
-	/* mode register of lpddram */
-	strb	r1, [r2, #0x33]
-
-	/* extended mode register of lpddrram */
-	ldr		r2, =0x81000000
-	strb	r1, [r2]
-
-	/* control | normal */
-	ldr	r1, =0x82216008
-	str	r1, [r0, #ESDRAMC_ESDCTL0]
-.endm
-
-.globl lowlevel_init
-lowlevel_init:
-	init_aips
-	init_max
-	init_clocks
-	init_lpddr
-	mov	pc, lr

+ 0 - 178
board/syteco/zmx25/zmx25.c

@@ -1,178 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (c) 2011 Graf-Syteco, Matthias Weisser
- * <weisserm@arcor.de>
- *
- * Based on tx25.c:
- * (C) Copyright 2009 DENX Software Engineering
- * Author: John Rigby <jrigby@gmail.com>
- *
- * Based on imx27lite.c:
- *   Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
- *   Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
- * And:
- *   RedBoot tx25_misc.c Copyright (C) 2009 Red Hat
- */
-#include <common.h>
-#include <cpu_func.h>
-#include <env.h>
-#include <init.h>
-#include <asm/global_data.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/iomux-mx25.h>
-#include <linux/delay.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_init()
-{
-	static const iomux_v3_cfg_t sdhc1_pads[] = {
-		NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL),
-		NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL),
-		NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL),
-		NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL),
-		NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL),
-		NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL),
-	};
-
-	static const iomux_v3_cfg_t dig_out_pads[] = {
-		MX25_PAD_CSI_D8__GPIO_1_7, /* Ouput 1 Ctrl */
-		MX25_PAD_CSI_D7__GPIO_1_6, /* Ouput 2 Ctrl */
-		NEW_PAD_CTRL(MX25_PAD_CSI_D6__GPIO_1_31, 0), /* Ouput 1 Stat */
-		NEW_PAD_CTRL(MX25_PAD_CSI_D5__GPIO_1_30, 0), /* Ouput 2 Stat */
-	};
-
-	static const iomux_v3_cfg_t led_pads[] = {
-		MX25_PAD_CSI_D9__GPIO_4_21,
-		MX25_PAD_CSI_D4__GPIO_1_29,
-	};
-
-	static const iomux_v3_cfg_t can_pads[] = {
-		NEW_PAD_CTRL(MX25_PAD_GPIO_A__CAN1_TX, NO_PAD_CTRL),
-		NEW_PAD_CTRL(MX25_PAD_GPIO_B__CAN1_RX, NO_PAD_CTRL),
-		NEW_PAD_CTRL(MX25_PAD_GPIO_C__CAN2_TX, NO_PAD_CTRL),
-		NEW_PAD_CTRL(MX25_PAD_GPIO_D__CAN2_RX, NO_PAD_CTRL),
-	};
-
-	static const iomux_v3_cfg_t i2c3_pads[] = {
-		MX25_PAD_CSPI1_SS1__I2C3_DAT,
-		MX25_PAD_GPIO_E__I2C3_CLK,
-	};
-
-	icache_enable();
-
-	/* Setup of core voltage selection pin to run at 1.4V */
-	imx_iomux_v3_setup_pad(MX25_PAD_EXT_ARMCLK__GPIO_3_15); /* VCORE */
-	gpio_direction_output(IMX_GPIO_NR(3, 15), 1);
-
-	/* Setup of SD card pins*/
-	imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
-
-	/* Setup of digital output for USB power and OC */
-	imx_iomux_v3_setup_pad(MX25_PAD_CSI_D3__GPIO_1_28); /* USB Power */
-	gpio_direction_output(IMX_GPIO_NR(1, 28), 1);
-
-	imx_iomux_v3_setup_pad(MX25_PAD_CSI_D2__GPIO_1_27); /* USB OC */
-	gpio_direction_input(IMX_GPIO_NR(1, 18));
-
-	/* Setup of digital output control pins */
-	imx_iomux_v3_setup_multiple_pads(dig_out_pads,
-						ARRAY_SIZE(dig_out_pads));
-
-	/* Switch both output drivers off */
-	gpio_direction_output(IMX_GPIO_NR(1, 7), 0);
-	gpio_direction_output(IMX_GPIO_NR(1, 6), 0);
-
-	/* Setup of key input pin */
-	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_KPP_ROW0__GPIO_2_29, 0));
-	gpio_direction_input(IMX_GPIO_NR(2, 29));
-
-	/* Setup of status LED outputs */
-	imx_iomux_v3_setup_multiple_pads(led_pads, ARRAY_SIZE(led_pads));
-
-	/* Switch both LEDs off */
-	gpio_direction_output(IMX_GPIO_NR(4, 21), 0);
-	gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
-
-	/* Setup of CAN1 and CAN2 signals */
-	imx_iomux_v3_setup_multiple_pads(can_pads, ARRAY_SIZE(can_pads));
-
-	/* Setup of I2C3 signals */
-	imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
-
-	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
-
-	return 0;
-}
-
-int board_late_init(void)
-{
-	const char *e;
-
-#ifdef CONFIG_FEC_MXC
-/*
- * FIXME: need to revisit this
- * The original code enabled PUE and 100-k pull-down without PKE, so the right
- * value here is likely:
- *	0 for no pull
- * or:
- *	PAD_CTL_PUS_100K_DOWN for 100-k pull-down
- */
-#define FEC_OUT_PAD_CTRL	0
-
-	static const iomux_v3_cfg_t fec_pads[] = {
-		MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
-		MX25_PAD_FEC_RX_DV__FEC_RX_DV,
-		MX25_PAD_FEC_RDATA0__FEC_RDATA0,
-		NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL),
-		NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL),
-		NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL),
-		MX25_PAD_FEC_MDIO__FEC_MDIO,
-		MX25_PAD_FEC_RDATA1__FEC_RDATA1,
-		NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL),
-
-		MX25_PAD_UPLL_BYPCLK__GPIO_3_16, /* LAN-RESET */
-		MX25_PAD_UART2_CTS__FEC_RX_ER, /* FEC_RX_ERR */
-	};
-
-	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
-
-	/* assert PHY reset (low) */
-	gpio_direction_output(IMX_GPIO_NR(3, 16), 0);
-
-	udelay(5000);
-
-	/* deassert PHY reset */
-	gpio_set_value(IMX_GPIO_NR(3, 16), 1);
-
-	udelay(5000);
-#endif
-
-	e = env_get("gs_base_board");
-	if (e != NULL) {
-		if (strcmp(e, "G283") == 0) {
-			int key = gpio_get_value(IMX_GPIO_NR(2, 29));
-
-			if (key) {
-				/* Switch on both LEDs to inidcate boot mode */
-				gpio_set_value(IMX_GPIO_NR(1, 29), 0);
-				gpio_set_value(IMX_GPIO_NR(4, 21), 0);
-
-				env_set("preboot", "run gs_slow_boot");
-			} else
-				env_set("preboot", "run gs_fast_boot");
-		}
-	}
-
-	return 0;
-}
-
-int dram_init(void)
-{
-	/* dram_init must store complete ramsize in gd->ram_size */
-	gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
-				PHYS_SDRAM_SIZE);
-	return 0;
-}

+ 0 - 38
configs/zmx25_defconfig

@@ -1,38 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MX25=y
-CONFIG_SYS_TEXT_BASE=0xA0000000
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_SECT_SIZE=0x20000
-CONFIG_TARGET_ZMX25=y
-CONFIG_IMX_CONFIG=""
-CONFIG_SYS_MALLOC_LEN=0x3f8000
-CONFIG_SYS_LOAD_ADDR=0x80000000
-CONFIG_BOOTDELAY=5
-CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="boot in %d s\n"
-CONFIG_AUTOBOOT_DELAY_STR="delaygs"
-CONFIG_AUTOBOOT_STOP_STR="stopgs"
-CONFIG_USE_PREBOOT=y
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_HUSH_PARSER=y
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_SYS_PROMPT="zmx25> "
-CONFIG_CMD_IMLS=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_ENV_ADDR=0xA0040000
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_MII=y
-CONFIG_MXC_UART=y
-CONFIG_USB=y
-CONFIG_LZO=y

+ 0 - 10
doc/imx/common/imx25.txt

@@ -1,10 +0,0 @@
-U-Boot for Freescale i.MX25
-
-This file contains information for the port of U-Boot to the Freescale i.MX25
-SoC.
-
-1. CONVENTIONS FOR FUSE ASSIGNMENTS
------------------------------------
-
-1.1 MAC Address: It is stored in the words 26 to 31 of fuse bank 0, using the
-    natural MAC byte order (i.e. MSB first).

+ 3 - 3
drivers/gpio/mxc_gpio.c

@@ -44,7 +44,7 @@ static unsigned long gpio_ports[] = {
 	[0] = GPIO1_BASE_ADDR,
 	[1] = GPIO2_BASE_ADDR,
 	[2] = GPIO3_BASE_ADDR,
-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
+#if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
 		defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
 		defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
 		defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050)
@@ -352,7 +352,7 @@ static const struct mxc_gpio_plat mxc_plat[] = {
 	{ 0, (struct gpio_regs *)GPIO1_BASE_ADDR },
 	{ 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
 	{ 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
+#if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
 		defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
 		defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
 	{ 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
@@ -376,7 +376,7 @@ U_BOOT_DRVINFOS(mxc_gpios) = {
 	{ "gpio_mxc", &mxc_plat[0] },
 	{ "gpio_mxc", &mxc_plat[1] },
 	{ "gpio_mxc", &mxc_plat[2] },
-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
+#if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
 		defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
 		defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
 	{ "gpio_mxc", &mxc_plat[3] },

+ 1 - 1
drivers/mtd/nand/raw/mxc_nand.c

@@ -11,7 +11,7 @@
 #include <linux/delay.h>
 #include <linux/err.h>
 #include <asm/io.h>
-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || \
+#if defined(CONFIG_MX27) || \
 	defined(CONFIG_MX51) || defined(CONFIG_MX53)
 #include <asm/arch/imx-regs.h>
 #endif

+ 0 - 5
drivers/mtd/nand/raw/mxc_nand.h

@@ -29,11 +29,6 @@
 #define is_mxc_nfc_1()		1
 #define is_mxc_nfc_21()		0
 #define is_mxc_nfc_32()		0
-#elif defined(CONFIG_MX25)
-#define MXC_NFC_V2_1
-#define is_mxc_nfc_1()		0
-#define is_mxc_nfc_21()		1
-#define is_mxc_nfc_32()		0
 #elif defined(CONFIG_MX51) || defined(CONFIG_MX53)
 #define MXC_NFC_V3
 #define MXC_NFC_V3_2

+ 1 - 1
drivers/net/fec_mxc.c

@@ -521,7 +521,7 @@ static int fec_open(struct eth_device *edev)
 	       &fec->eth->ecntrl);
 #endif
 
-#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
 	udelay(100);
 
 	/* setup the MII gasket for RMII mode */

+ 2 - 2
drivers/net/fec_mxc.h

@@ -128,7 +128,7 @@ struct ethernet_regs {
 
 	uint32_t res14[7];		/* MBAR_ETH + 0x2E4-2FC */
 
-#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
 	uint16_t miigsk_cfgr;		/* MBAR_ETH + 0x300 */
 	uint16_t res15[3];		/* MBAR_ETH + 0x302-306 */
 	uint16_t miigsk_enr;		/* MBAR_ETH + 0x308 */
@@ -196,7 +196,7 @@ struct ethernet_regs {
 #define FEC_X_DES_ACTIVE_TDAR		0x01000000
 #define FEC_R_DES_ACTIVE_RDAR		0x01000000
 
-#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
+#if defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
 /* defines for MIIGSK */
 /* RMII frequency control: 0=50MHz, 1=5MHz */
 #define MIIGSK_CFGR_FRCONT		(1 << 6)

+ 1 - 1
drivers/serial/Kconfig

@@ -645,7 +645,7 @@ config MCFUART
 
 config MXC_UART
 	bool "IMX serial port support"
-	depends on ARCH_MX25 || ARCH_MX31 || MX5 || MX6 || MX7 || IMX8M
+	depends on ARCH_MX31 || MX5 || MX6 || MX7 || IMX8M
 	help
 	  If you have a machine based on a Motorola IMX CPU you
 	  can enable its onboard serial port by enabling this option.

+ 1 - 8
drivers/spi/mxc_spi.c

@@ -23,7 +23,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* MX35 and older is CSPI */
-#if defined(CONFIG_MX25) || defined(CONFIG_MX31)
+#if defined(CONFIG_MX31)
 #define MXC_CSPI
 struct cspi_regs {
 	u32 rxdata;
@@ -48,17 +48,10 @@ struct cspi_regs {
 #define MXC_CSPICTRL_RXOVF		BIT(6)
 #define MXC_CSPIPERIOD_32KHZ		BIT(15)
 #define MAX_SPI_BYTES			4
-#if defined(CONFIG_MX25)
-#define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 12)
-#define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0xfff) << 20)
-#define MXC_CSPICTRL_TC			BIT(7)
-#define MXC_CSPICTRL_MAXBITS		0xfff
-#else	/* MX31 */
 #define MXC_CSPICTRL_CHIPSELECT(x)	(((x) & 0x3) << 24)
 #define MXC_CSPICTRL_BITCOUNT(x)	(((x) & 0x1f) << 8)
 #define MXC_CSPICTRL_TC			BIT(8)
 #define MXC_CSPICTRL_MAXBITS		0x1f
-#endif
 
 #else	/* MX51 and newer is ECSPI */
 #define MXC_ECSPI

+ 1 - 50
drivers/usb/host/ehci-mxc.c

@@ -67,56 +67,7 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
 	unsigned int v;
 
 	v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
-#if defined(CONFIG_MX25)
-	switch (port) {
-	case 0:	/* OTG port */
-		v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
-				MX25_OTG_OCPOL_BIT);
-		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
-
-		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-			v |= MX25_OTG_PM_BIT;
-
-		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
-			v |= MX25_OTG_PP_BIT;
-
-		if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
-			v |= MX25_OTG_OCPOL_BIT;
-
-		break;
-	case 1: /* H1 port */
-		v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |
-				MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT |
-				MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT |
-				MX25_H1_IPPUE_UP_BIT);
-		v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
-
-		if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
-			v |= MX25_H1_PM_BIT;
-
-		if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
-			v |= MX25_H1_PP_BIT;
-
-		if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
-			v |= MX25_H1_OCPOL_BIT;
-
-		if (!(flags & MXC_EHCI_TTL_ENABLED))
-			v |= MX25_H1_TLL_BIT;
-
-		if (flags & MXC_EHCI_INTERNAL_PHY)
-			v |= MX25_H1_USBTE_BIT;
-
-		if (flags & MXC_EHCI_IPPUE_DOWN)
-			v |= MX25_H1_IPPUE_DOWN_BIT;
-
-		if (flags & MXC_EHCI_IPPUE_UP)
-			v |= MX25_H1_IPPUE_UP_BIT;
-
-		break;
-	default:
-		return -EINVAL;
-	}
-#elif defined(CONFIG_MX31)
+#if defined(CONFIG_MX31)
 	switch (port) {
 	case 0:	/* OTG port */
 		v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);

+ 1 - 1
drivers/w1/Kconfig

@@ -20,7 +20,7 @@ config W1_GPIO
 
 config W1_MXC
 	bool "Enable 1-wire controller on i.MX processors"
-	depends on ARCH_MX25 || ARCH_MX31 || ARCH_MX5
+	depends on ARCH_MX31 || ARCH_MX5
 	help
 	  Support the one wire controller found in some members of the NXP
 	  i.MX SoC family.

+ 1 - 1
drivers/watchdog/Kconfig

@@ -24,7 +24,7 @@ config WATCHDOG_AUTOSTART
 
 config WATCHDOG_TIMEOUT_MSECS
 	int "Watchdog timeout in msec"
-	default 128000 if ARCH_MX25 || ARCH_MX31 || ARCH_MX5 || ARCH_MX6
+	default 128000 if ARCH_MX31 || ARCH_MX5 || ARCH_MX6
 	default 128000 if ARCH_MX7 || ARCH_VF610
 	default 30000 if ARCH_SOCFPGA
 	default 60000

+ 0 - 78
include/configs/zmx25.h

@@ -1,78 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (c) 2011 Graf-Syteco, Matthias Weisser
- * <weisserm@arcor.de>
- *
- * Configuation settings for the zmx25 board
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-
-#define CONFIG_SYS_TIMER_RATE		32768
-#define CONFIG_SYS_TIMER_COUNTER	\
-	(&((struct gpt_regs *)IMX_GPT1_BASE)->counter)
-
-/*
- * Environment settings
- */
-#define CONFIG_EXTRA_ENV_SETTINGS \
-	"gs_fast_boot=setenv bootdelay 5\0" \
-	"gs_slow_boot=setenv bootdelay 10\0" \
-	"bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \
-		"fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \
-		"bootm 0x81000000; bootelf 0x81000000\0"
-
-/*
- * Hardware drivers
- */
-
-/*
- * Serial
- */
-#define CONFIG_MXC_UART_BASE	UART2_BASE
-
-/*
- * Ethernet
- */
-#define CONFIG_FEC_MXC
-#define CONFIG_FEC_MXC_PHYADDR		0x00
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-/*
- * USB
- */
-#ifdef CONFIG_CMD_USB
-#define CONFIG_USB_EHCI_MXC
-#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
-#define CONFIG_MXC_USB_PORT	1
-#define CONFIG_MXC_USB_PORTSC	PORT_PTS_SERIAL
-#define CONFIG_MXC_USB_FLAGS	(MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN)
-#define CONFIG_EHCI_IS_TDI
-#endif /* CONFIG_CMD_USB */
-
-/* SDRAM */
-#define PHYS_SDRAM		0x80000000	/* start address of LPDDRRAM */
-#define PHYS_SDRAM_SIZE		0x04000000	/* 64 megs */
-
-#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM
-#define CONFIG_SYS_INIT_SP_ADDR	0x78020000	/* end of internal SRAM */
-
-/*
- * FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_BASE		0xA0000000
-#define CONFIG_SYS_MAX_FLASH_BANKS	1
-#define CONFIG_SYS_MAX_FLASH_SECT	256
-
-/*
- * CFI FLASH driver setup
- */
-
-#endif	/* __CONFIG_H */