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@@ -56,3 +56,33 @@ int board_early_init_f(void)
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return 0;
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}
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+
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+#ifdef CONFIG_ISA_ARCV2
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+#define RESET_VECTOR_ADDR 0x0
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+
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+void smp_set_core_boot_addr(unsigned long addr, int corenr)
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+{
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+ /* All cores have reset vector pointing to 0 */
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+ writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
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+
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+ /* Make sure other cores see written value in memory */
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+ flush_dcache_range(RESET_VECTOR_ADDR, RESET_VECTOR_ADDR + sizeof(int));
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+}
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+
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+void smp_kick_all_cpus(void)
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+{
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+/* CPU start CREG */
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+#define AXC003_CREG_CPU_START 0xF0001400
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+
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+/* Bits positions in CPU start CREG */
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+#define BITS_START 0
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+#define BITS_POLARITY 8
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+#define BITS_CORE_SEL 9
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+#define BITS_MULTICORE 12
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+
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+#define CMD (1 << BITS_MULTICORE) | (1 << BITS_CORE_SEL) | \
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+ (1 << BITS_POLARITY) | (1 << BITS_START)
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+
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+ writel(CMD, (void __iomem *)AXC003_CREG_CPU_START);
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+}
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+#endif
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