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board: starfive: jh7110: Add cpu voltage set commands

Get the binning information from OTP,
and set change the cpu max voltage accordingly.

Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
Mason Huo 1 éve
szülő
commit
8847bc69aa

+ 38 - 0
board/starfive/visionfive2/starfive_visionfive2.c

@@ -27,6 +27,8 @@
 #define PCB_REVISION_B		0x0B
 #define CHIP_REVISION_SHIFT	80
 
+#define CPU_VOL_BINNING_OFFSET 0x7fc
+
 enum {
 	BOOT_FLASH =	0,
 	BOOT_SD,
@@ -46,6 +48,13 @@ enum board_type_t {
 	BOARD_TYPE_MAX,
 };
 
+
+enum cpu_voltage_type_t {
+	CPU_VOL_1040 = 0xff,
+	CPU_VOL_1060 = 0xf0,
+	CPU_VOL_1080 = 0xf1,
+};
+
 static void sys_reset_clear(ulong assert, ulong status, u32 rst)
 {
 	u32 value;
@@ -287,6 +296,32 @@ static void jh7110_usb_init(bool usb2_enable)
 	SYS_IOMUX_DOUT(25, 7);
 }
 
+#if CONFIG_IS_ENABLED(STARFIVE_OTP)
+static void get_cpu_voltage_type(struct udevice *dev)
+{
+	int ret;
+	u32 buf = CPU_VOL_1040;
+
+	ret = misc_read(dev, CPU_VOL_BINNING_OFFSET, &buf, sizeof(buf));
+	if (ret != sizeof(buf))
+		printf("%s: error reading CPU vol from OTP\n", __func__);
+	else {
+		switch ((buf & 0xff)) {
+		case CPU_VOL_1080:
+			env_set("cpu_max_vol", "1080000");
+			break;
+		case CPU_VOL_1060:
+			env_set("cpu_max_vol", "1060000");
+			break;
+		case CPU_VOL_1040:
+		default:
+			env_set("cpu_max_vol", "1040000");
+			break;
+		}
+	}
+}
+#endif
+
 /*enable U74-mc hart1~hart4 prefetcher*/
 static void enable_prefetcher(void)
 {
@@ -452,6 +487,9 @@ err:
 
 	get_chip_type();
 	set_uboot_fdt_addr_env();
+#if CONFIG_IS_ENABLED(STARFIVE_OTP)
+	get_cpu_voltage_type(dev);
+#endif
 	return 0;
 }
 #endif

+ 1 - 1
drivers/misc/Kconfig

@@ -77,7 +77,7 @@ config SIFIVE_OTP
 
 config STARFIVE_OTP
         bool "StarFive eFuse OTP driver"
-        depends on MISC && !ID_EEPROM
+        depends on MISC
         help
           Enable support for reading and writing the eFuse OTP on the
           StarFive SoCs.

+ 26 - 0
include/configs/starfive-visionfive2.h

@@ -96,6 +96,28 @@
 #define TYPE_GUID_LOADER2	"2E54B353-1271-4842-806F-E436D6AF6985"
 #define TYPE_GUID_SYSTEM	"0FC63DAF-8483-4772-8E79-3D69D8477DE4"
 
+#define CPU_VOL_1040_SET \
+	"cpu_vol_1040_set="			\
+	"fdt set /opp-table-0/opp-1500000000 opp-microvolt <1040000>;\0"
+
+#define CPU_VOL_1060_SET \
+	"cpu_vol_1060_set="			\
+	"fdt set /opp-table-0/opp-1500000000 opp-microvolt <1060000>;\0"
+
+#define CPU_VOL_1080_SET \
+	"cpu_vol_1080_set="			\
+	"fdt set /opp-table-0/opp-1500000000 opp-microvolt <1080000>;\0"
+
+#define CPU_VOL_SET	\
+	"cpu_vol_set="				\
+	"if test ${cpu_max_vol} = 1080000; then "		\
+		"run cpu_vol_1080_set;"			\
+	"elif test ${cpu_max_vol} = 1060000; then "	\
+		"run cpu_vol_1060_set;"			\
+	"else "						\
+		"run cpu_vol_1040_set;"			\
+	"fi; \0"
+
 #define VF2_DISTRO_BOOTENV \
 	"fatbootpart=1:3\0"	\
 	"distroloadaddr=0xb0000000\0"	\
@@ -216,6 +238,10 @@
 	VISIONFIVE2_BOOTENV				\
 	CHIPA_GMAC_SET					\
 	CHIPA_SET					\
+	CPU_VOL_1040_SET				\
+	CPU_VOL_1060_SET				\
+	CPU_VOL_1080_SET				\
+	CPU_VOL_SET					\
 	CHIPA_SET_FORCE					\
 	VISIONFIVE2_MEM_SET				\
 	"type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \