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@@ -22,14 +22,16 @@
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#define STARFIVE_CLK_MUX_SHIFT 24 /*[29:24]*/
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#define STARFIVE_CLK_DIV_SHIFT 0 /*[23:0]*/
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-#define SYS_OFFSET(id) (id * 4)
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-#define STG_OFFSET(id) ((id - JH7110_CLK_SYS_REG_END) * 4)
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-#define AON_OFFSET(id) ((id - JH7110_CLK_STG_REG_END) * 4)
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+#define SYS_OFFSET(id) ((id) * 4)
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+#define STG_OFFSET(id) (((id) - JH7110_CLK_SYS_REG_END) * 4)
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+#define AON_OFFSET(id) (((id) - JH7110_CLK_STG_REG_END) * 4)
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+#define VOUT_OFFSET(id) (((id) - JH7110_CLK_VOUT_START) * 4)
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struct jh7110_clk_priv {
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void __iomem *sys;
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void __iomem *stg;
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void __iomem *aon;
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+ void __iomem *vout;
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};
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static const char *cpu_root_sels[2] = {
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@@ -62,6 +64,31 @@ static const char *u0_dw_gmac5_axi64_clk_tx_sels[2] = {
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[1] = "gmac0_rmii_rtx",
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};
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+static const char *mclk_sels[2] = {
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+ [0] = "mclk_inner",
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+ [1] = "mclk_ext",
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+};
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+
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+static const char *u0_i2stx_4ch_bclk_sels[2] = {
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+ [0] = "i2stx_4ch0_bclk_mst",
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+ [1] = "i2stx_bclk_ext",
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+};
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+
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+static const char *u0_dc8200_clk_pix_sels[2] = {
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+ [0] = "dc8200_pix0",
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+ [1] = "hdmitx0_pixelclk",
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+};
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+
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+static const char *dom_vout_top_lcd_clk_sels[2] = {
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+ [0] = "u0_dc8200_clk_pix0_out",
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+ [1] = "u0_dc8200_clk_pix1_out",
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+};
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+
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+static const char *u0_cdns_dsitx_clk_sels[2] = {
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+ [0] = "dc8200_pix0",
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+ [1] = "hdmitx0_pixelclk",
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+};
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+
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static ulong starfive_clk_get_rate(struct clk *clk)
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{
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struct clk *c;
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@@ -310,303 +337,497 @@ static int jh7110_clk_init(struct udevice *dev)
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pll = starfive_jh7110_pll_get_rate(PLL0, &conf);
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clk_dm(JH7110_PLL0_OUT,
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- starfive_clk_fix_factor(priv->sys,
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- "pll0_out", "osc", conf.fbdiv, conf.prediv * conf.postdiv1));
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+ starfive_clk_fix_factor(priv->sys,
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+ "pll0_out", "osc", conf.fbdiv,
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+ conf.prediv * conf.postdiv1));
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pll = starfive_jh7110_pll_get_rate(PLL1, &conf);
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clk_dm(JH7110_PLL1_OUT,
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- starfive_clk_fix_factor(priv->sys,
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- "pll1_out", "osc", conf.fbdiv, conf.prediv * conf.postdiv1));
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+ starfive_clk_fix_factor(priv->sys,
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+ "pll1_out", "osc", conf.fbdiv,
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+ conf.prediv * conf.postdiv1));
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pll = starfive_jh7110_pll_get_rate(PLL2, &conf);
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clk_dm(JH7110_PLL2_OUT,
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- starfive_clk_fix_factor(priv->sys,
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- "pll2_out", "osc", conf.fbdiv, conf.prediv * conf.postdiv1));
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+ starfive_clk_fix_factor(priv->sys,
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+ "pll2_out", "osc", conf.fbdiv,
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+ conf.prediv * conf.postdiv1));
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/*root*/
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clk_dm(JH7110_CPU_ROOT,
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- starfive_clk_mux(priv->sys, "cpu_root",
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- SYS_OFFSET(JH7110_CPU_ROOT), 1,
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- cpu_root_sels, ARRAY_SIZE(cpu_root_sels)));
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+ starfive_clk_mux(priv->sys, "cpu_root",
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+ SYS_OFFSET(JH7110_CPU_ROOT), 1,
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+ cpu_root_sels, ARRAY_SIZE(cpu_root_sels)));
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clk_dm(JH7110_CPU_CORE,
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- starfive_clk_divider(priv->sys,
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- "cpu_core", "cpu_root",
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- SYS_OFFSET(JH7110_CPU_CORE), 3));
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+ starfive_clk_divider(priv->sys,
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+ "cpu_core", "cpu_root",
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+ SYS_OFFSET(JH7110_CPU_CORE), 3));
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clk_dm(JH7110_CPU_BUS,
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- starfive_clk_divider(priv->sys,
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- "cpu_bus", "cpu_core",
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- SYS_OFFSET(JH7110_CPU_BUS), 2));
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+ starfive_clk_divider(priv->sys,
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+ "cpu_bus", "cpu_core",
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+ SYS_OFFSET(JH7110_CPU_BUS), 2));
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clk_dm(JH7110_DDR_ROOT,
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- starfive_clk_fix_factor(priv->sys,
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- "ddr_root", "pll1_out", 1, 1));
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+ starfive_clk_fix_factor(priv->sys,
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+ "ddr_root", "pll1_out", 1, 1));
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clk_dm(JH7110_GMACUSB_ROOT,
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- starfive_clk_fix_factor(priv->sys,
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- "gmacusb_root", "pll0_out", 1, 1));
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+ starfive_clk_fix_factor(priv->sys,
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+ "gmacusb_root", "pll0_out", 1, 1));
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clk_dm(JH7110_PERH_ROOT,
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- starfive_clk_composite(priv->sys,
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- "perh_root",
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- perh_root_sels, ARRAY_SIZE(perh_root_sels),
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- SYS_OFFSET(JH7110_PERH_ROOT), 1, 0, 2));
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+ starfive_clk_composite(priv->sys,
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+ "perh_root",
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+ perh_root_sels, ARRAY_SIZE(perh_root_sels),
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+ SYS_OFFSET(JH7110_PERH_ROOT), 1, 0, 2));
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clk_dm(JH7110_BUS_ROOT,
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- starfive_clk_mux(priv->sys, "bus_root",
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- SYS_OFFSET(JH7110_BUS_ROOT), 1,
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- bus_root_sels, ARRAY_SIZE(bus_root_sels)));
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+ starfive_clk_mux(priv->sys, "bus_root",
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+ SYS_OFFSET(JH7110_BUS_ROOT), 1,
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+ bus_root_sels, ARRAY_SIZE(bus_root_sels)));
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clk_dm(JH7110_AXI_CFG0,
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- starfive_clk_divider(priv->sys,
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- "axi_cfg0", "bus_root",
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- SYS_OFFSET(JH7110_AXI_CFG0), 2));
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+ starfive_clk_divider(priv->sys,
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+ "axi_cfg0", "bus_root",
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+ SYS_OFFSET(JH7110_AXI_CFG0), 2));
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clk_dm(JH7110_STG_AXIAHB,
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- starfive_clk_divider(priv->sys,
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- "stg_axiahb", "axi_cfg0",
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- SYS_OFFSET(JH7110_STG_AXIAHB), 2));
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+ starfive_clk_divider(priv->sys,
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+ "stg_axiahb", "axi_cfg0",
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+ SYS_OFFSET(JH7110_STG_AXIAHB), 2));
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clk_dm(JH7110_AHB0,
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- starfive_clk_gate(priv->sys,
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- "ahb0", "stg_axiahb",
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- SYS_OFFSET(JH7110_AHB0)));
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+ starfive_clk_gate(priv->sys,
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+ "ahb0", "stg_axiahb",
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+ SYS_OFFSET(JH7110_AHB0)));
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clk_dm(JH7110_AHB1,
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- starfive_clk_gate(priv->sys,
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- "ahb1", "stg_axiahb",
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- SYS_OFFSET(JH7110_AHB1)));
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+ starfive_clk_gate(priv->sys,
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+ "ahb1", "stg_axiahb",
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+ SYS_OFFSET(JH7110_AHB1)));
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clk_dm(JH7110_APB_BUS_FUNC,
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- starfive_clk_divider(priv->sys,
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- "apb_bus_func", "stg_axiahb",
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- SYS_OFFSET(JH7110_APB_BUS_FUNC), 4));
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+ starfive_clk_divider(priv->sys,
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+ "apb_bus_func", "stg_axiahb",
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+ SYS_OFFSET(JH7110_APB_BUS_FUNC), 4));
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clk_dm(JH7110_PCLK2_MUX_FUNC_PCLK,
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- starfive_clk_fix_factor(priv->sys,
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- "u2_pclk_mux_func_pclk", "apb_bus_func", 1, 1));
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+ starfive_clk_fix_factor(priv->sys,
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+ "u2_pclk_mux_func_pclk", "apb_bus_func", 1, 1));
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clk_dm(JH7110_U2_PCLK_MUX_PCLK,
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- starfive_clk_fix_factor(priv->sys,
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- "u2_pclk_mux_pclk", "u2_pclk_mux_func_pclk", 1, 1));
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+ starfive_clk_fix_factor(priv->sys,
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+ "u2_pclk_mux_pclk", "u2_pclk_mux_func_pclk", 1, 1));
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clk_dm(JH7110_APB_BUS,
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- starfive_clk_fix_factor(priv->sys,
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- "apb_bus", "u2_pclk_mux_pclk", 1, 1));
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+ starfive_clk_fix_factor(priv->sys,
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+ "apb_bus", "u2_pclk_mux_pclk", 1, 1));
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clk_dm(JH7110_APB0,
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- starfive_clk_gate(priv->sys,
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- "apb0", "apb_bus",
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- SYS_OFFSET(JH7110_APB0)));
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+ starfive_clk_gate(priv->sys,
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+ "apb0", "apb_bus",
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+ SYS_OFFSET(JH7110_APB0)));
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clk_dm(JH7110_APB12,
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- starfive_clk_fix_factor(priv->sys,
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- "apb12", "apb_bus", 1, 1));
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+ starfive_clk_fix_factor(priv->sys,
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+ "apb12", "apb_bus", 1, 1));
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clk_dm(JH7110_AON_APB,
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- starfive_clk_fix_factor(priv->sys,
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- "aon_apb", "apb_bus_func", 1, 1));
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+ starfive_clk_fix_factor(priv->sys,
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+ "aon_apb", "apb_bus_func", 1, 1));
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/*QSPI*/
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clk_dm(JH7110_QSPI_CLK_AHB,
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- starfive_clk_gate(priv->sys,
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- "u0_cdns_qspi_clk_ahb", "ahb1",
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- SYS_OFFSET(JH7110_QSPI_CLK_AHB)));
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+ starfive_clk_gate(priv->sys,
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+ "u0_cdns_qspi_clk_ahb", "ahb1",
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+ SYS_OFFSET(JH7110_QSPI_CLK_AHB)));
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clk_dm(JH7110_QSPI_CLK_APB,
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- starfive_clk_gate(priv->sys,
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- "u0_cdns_qspi_clk_apb", "apb12",
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- SYS_OFFSET(JH7110_QSPI_CLK_APB)));
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+ starfive_clk_gate(priv->sys,
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+ "u0_cdns_qspi_clk_apb", "apb12",
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+ SYS_OFFSET(JH7110_QSPI_CLK_APB)));
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clk_dm(JH7110_QSPI_REF_SRC,
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- starfive_clk_divider(priv->sys,
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- "u0_cdns_qspi_ref_src", "gmacusb_root",
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- SYS_OFFSET(JH7110_QSPI_REF_SRC), 5));
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+ starfive_clk_divider(priv->sys,
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+ "u0_cdns_qspi_ref_src", "gmacusb_root",
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+ SYS_OFFSET(JH7110_QSPI_REF_SRC), 5));
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clk_dm(JH7110_QSPI_CLK_REF,
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- starfive_clk_composite(priv->sys,
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- "u0_cdns_qspi_clk_ref",
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- qspi_ref_sels, ARRAY_SIZE(qspi_ref_sels),
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- SYS_OFFSET(JH7110_QSPI_CLK_REF), 1, 1, 0));
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+ starfive_clk_composite(priv->sys,
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+ "u0_cdns_qspi_clk_ref",
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+ qspi_ref_sels, ARRAY_SIZE(qspi_ref_sels),
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+ SYS_OFFSET(JH7110_QSPI_CLK_REF), 1, 1, 0));
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/*SDIO*/
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clk_dm(JH7110_SDIO0_CLK_AHB,
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- starfive_clk_gate(priv->sys,
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- "u0_dw_sdio_clk_ahb", "ahb0",
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- SYS_OFFSET(JH7110_SDIO0_CLK_AHB)));
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+ starfive_clk_gate(priv->sys,
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+ "u0_dw_sdio_clk_ahb", "ahb0",
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+ SYS_OFFSET(JH7110_SDIO0_CLK_AHB)));
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clk_dm(JH7110_SDIO1_CLK_AHB,
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- starfive_clk_gate(priv->sys,
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- "u1_dw_sdio_clk_ahb", "ahb0",
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- SYS_OFFSET(JH7110_SDIO1_CLK_AHB)));
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+ starfive_clk_gate(priv->sys,
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+ "u1_dw_sdio_clk_ahb", "ahb0",
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+ SYS_OFFSET(JH7110_SDIO1_CLK_AHB)));
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clk_dm(JH7110_SDIO0_CLK_SDCARD,
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- starfive_clk_fix_parent_composite(priv->sys,
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- "u0_dw_sdio_clk_sdcard", "axi_cfg0",
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- SYS_OFFSET(JH7110_SDIO0_CLK_SDCARD), 0, 1, 4));
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+ starfive_clk_fix_parent_composite(priv->sys,
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+ "u0_dw_sdio_clk_sdcard", "axi_cfg0",
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+ SYS_OFFSET(JH7110_SDIO0_CLK_SDCARD), 0, 1, 4));
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clk_dm(JH7110_SDIO1_CLK_SDCARD,
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- starfive_clk_fix_parent_composite(priv->sys,
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- "u1_dw_sdio_clk_sdcard", "axi_cfg0",
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- SYS_OFFSET(JH7110_SDIO1_CLK_SDCARD), 0, 1, 4));
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+ starfive_clk_fix_parent_composite(priv->sys,
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+ "u1_dw_sdio_clk_sdcard", "axi_cfg0",
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+ SYS_OFFSET(JH7110_SDIO1_CLK_SDCARD), 0, 1, 4));
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/*STG*/
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clk_dm(JH7110_USB_125M,
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- starfive_clk_divider(priv->sys,
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- "usb_125m", "gmacusb_root",
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- SYS_OFFSET(JH7110_USB_125M), 4));
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+ starfive_clk_divider(priv->sys,
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+ "usb_125m", "gmacusb_root",
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+ SYS_OFFSET(JH7110_USB_125M), 4));
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/*GMAC1*/
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clk_dm(JH7110_GMAC5_CLK_AHB,
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- starfive_clk_gate(priv->sys,
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- "u1_dw_gmac5_axi64_clk_ahb", "ahb0",
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- SYS_OFFSET(JH7110_GMAC5_CLK_AHB)));
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+ starfive_clk_gate(priv->sys,
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+ "u1_dw_gmac5_axi64_clk_ahb", "ahb0",
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+ SYS_OFFSET(JH7110_GMAC5_CLK_AHB)));
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clk_dm(JH7110_GMAC5_CLK_AXI,
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- starfive_clk_gate(priv->sys,
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- "u1_dw_gmac5_axi64_clk_axi", "stg_axiahb",
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- SYS_OFFSET(JH7110_GMAC5_CLK_AXI)));
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+ starfive_clk_gate(priv->sys,
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+ "u1_dw_gmac5_axi64_clk_axi", "stg_axiahb",
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+ SYS_OFFSET(JH7110_GMAC5_CLK_AXI)));
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clk_dm(JH7110_GMAC_SRC,
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- starfive_clk_divider(priv->sys,
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- "gmac_src", "gmacusb_root",
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- SYS_OFFSET(JH7110_GMAC_SRC), 3));
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+ starfive_clk_divider(priv->sys,
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+ "gmac_src", "gmacusb_root",
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+ SYS_OFFSET(JH7110_GMAC_SRC), 3));
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clk_dm(JH7110_GMAC1_GTXCLK,
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- starfive_clk_divider(priv->sys,
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- "gmac1_gtxclk", "gmacusb_root",
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- SYS_OFFSET(JH7110_GMAC1_GTXCLK), 4));
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+ starfive_clk_divider(priv->sys,
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+ "gmac1_gtxclk", "gmacusb_root",
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+ SYS_OFFSET(JH7110_GMAC1_GTXCLK), 4));
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clk_dm(JH7110_GMAC1_GTXC,
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- starfive_clk_gate(priv->sys,
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- "gmac1_gtxc", "gmac1_gtxclk",
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- SYS_OFFSET(JH7110_GMAC1_GTXC)));
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+ starfive_clk_gate(priv->sys,
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+ "gmac1_gtxc", "gmac1_gtxclk",
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+ SYS_OFFSET(JH7110_GMAC1_GTXC)));
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clk_dm(JH7110_GMAC1_RMII_RTX,
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- starfive_clk_divider(priv->sys,
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- "gmac1_rmii_rtx", "gmac1_rmii_refin",
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- SYS_OFFSET(JH7110_GMAC1_RMII_RTX), 5));
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+ starfive_clk_divider(priv->sys,
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+ "gmac1_rmii_rtx", "gmac1_rmii_refin",
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+ SYS_OFFSET(JH7110_GMAC1_RMII_RTX), 5));
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clk_dm(JH7110_GMAC5_CLK_PTP,
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- starfive_clk_gate_divider(priv->sys,
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- "u1_dw_gmac5_axi64_clk_ptp", "gmac_src",
|
|
|
- SYS_OFFSET(JH7110_GMAC5_CLK_PTP), 5));
|
|
|
+ starfive_clk_gate_divider(priv->sys,
|
|
|
+ "u1_dw_gmac5_axi64_clk_ptp", "gmac_src",
|
|
|
+ SYS_OFFSET(JH7110_GMAC5_CLK_PTP), 5));
|
|
|
clk_dm(JH7110_GMAC5_CLK_TX,
|
|
|
- starfive_clk_composite(priv->sys,
|
|
|
- "u1_dw_gmac5_axi64_clk_tx",
|
|
|
- gmac5_tx_sels, ARRAY_SIZE(gmac5_tx_sels),
|
|
|
- SYS_OFFSET(JH7110_GMAC5_CLK_TX), 1, 1, 0));
|
|
|
+ starfive_clk_composite(priv->sys,
|
|
|
+ "u1_dw_gmac5_axi64_clk_tx",
|
|
|
+ gmac5_tx_sels, ARRAY_SIZE(gmac5_tx_sels),
|
|
|
+ SYS_OFFSET(JH7110_GMAC5_CLK_TX), 1, 1, 0));
|
|
|
/*GMAC0*/
|
|
|
clk_dm(JH7110_AON_AHB,
|
|
|
- starfive_clk_fix_factor(priv->sys, "aon_ahb",
|
|
|
- "stg_axiahb", 1, 1));
|
|
|
+ starfive_clk_fix_factor(priv->sys, "aon_ahb",
|
|
|
+ "stg_axiahb", 1, 1));
|
|
|
clk_dm(JH7110_GMAC0_GTXCLK,
|
|
|
- starfive_clk_gate_divider(priv->sys, "gmac0_gtxclk",
|
|
|
- "gmacusb_root", SYS_OFFSET(JH7110_GMAC0_GTXCLK), 4));
|
|
|
+ starfive_clk_gate_divider(priv->sys, "gmac0_gtxclk",
|
|
|
+ "gmacusb_root", SYS_OFFSET(JH7110_GMAC0_GTXCLK), 4));
|
|
|
clk_dm(JH7110_GMAC0_PTP,
|
|
|
- starfive_clk_gate_divider(priv->sys, "gmac0_ptp",
|
|
|
- "gmac_src", SYS_OFFSET(JH7110_GMAC0_PTP), 5));
|
|
|
+ starfive_clk_gate_divider(priv->sys, "gmac0_ptp",
|
|
|
+ "gmac_src", SYS_OFFSET(JH7110_GMAC0_PTP), 5));
|
|
|
clk_dm(JH7110_GMAC0_GTXC,
|
|
|
- starfive_clk_gate(priv->sys,
|
|
|
- "gmac0_gtxc", "gmac0_gtxclk",
|
|
|
- SYS_OFFSET(JH7110_GMAC0_GTXC)));
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "gmac0_gtxc", "gmac0_gtxclk",
|
|
|
+ SYS_OFFSET(JH7110_GMAC0_GTXC)));
|
|
|
/*UART0*/
|
|
|
clk_dm(JH7110_UART0_CLK_APB,
|
|
|
- starfive_clk_gate(priv->sys,
|
|
|
- "u0_dw_uart_clk_apb", "apb0",
|
|
|
- SYS_OFFSET(JH7110_UART0_CLK_APB)));
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u0_dw_uart_clk_apb", "apb0",
|
|
|
+ SYS_OFFSET(JH7110_UART0_CLK_APB)));
|
|
|
clk_dm(JH7110_UART0_CLK_CORE,
|
|
|
- starfive_clk_gate(priv->sys,
|
|
|
- "u0_dw_uart_clk_core", "osc",
|
|
|
- SYS_OFFSET(JH7110_UART0_CLK_CORE)));
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u0_dw_uart_clk_core", "osc",
|
|
|
+ SYS_OFFSET(JH7110_UART0_CLK_CORE)));
|
|
|
|
|
|
/*UART1*/
|
|
|
clk_dm(JH7110_UART1_CLK_APB,
|
|
|
- starfive_clk_gate(priv->sys,
|
|
|
- "u1_dw_uart_clk_apb", "apb0",
|
|
|
- SYS_OFFSET(JH7110_UART1_CLK_APB)));
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u1_dw_uart_clk_apb", "apb0",
|
|
|
+ SYS_OFFSET(JH7110_UART1_CLK_APB)));
|
|
|
clk_dm(JH7110_UART1_CLK_CORE,
|
|
|
- starfive_clk_gate(priv->sys,
|
|
|
- "u1_dw_uart_clk_core", "osc",
|
|
|
- SYS_OFFSET(JH7110_UART1_CLK_CORE)));
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u1_dw_uart_clk_core", "osc",
|
|
|
+ SYS_OFFSET(JH7110_UART1_CLK_CORE)));
|
|
|
|
|
|
/*UART2*/
|
|
|
clk_dm(JH7110_UART2_CLK_APB,
|
|
|
- starfive_clk_gate(priv->sys,
|
|
|
- "u2_dw_uart_clk_apb", "apb0",
|
|
|
- SYS_OFFSET(JH7110_UART2_CLK_APB)));
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u2_dw_uart_clk_apb", "apb0",
|
|
|
+ SYS_OFFSET(JH7110_UART2_CLK_APB)));
|
|
|
clk_dm(JH7110_UART2_CLK_CORE,
|
|
|
- starfive_clk_gate(priv->sys,
|
|
|
- "u2_dw_uart_clk_core", "osc",
|
|
|
- SYS_OFFSET(JH7110_UART2_CLK_CORE)));
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u2_dw_uart_clk_core", "osc",
|
|
|
+ SYS_OFFSET(JH7110_UART2_CLK_CORE)));
|
|
|
|
|
|
/*UART3*/
|
|
|
clk_dm(JH7110_UART3_CLK_APB,
|
|
|
- starfive_clk_gate(priv->sys,
|
|
|
- "u3_dw_uart_clk_apb", "apb0",
|
|
|
- SYS_OFFSET(JH7110_UART3_CLK_APB)));
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u3_dw_uart_clk_apb", "apb0",
|
|
|
+ SYS_OFFSET(JH7110_UART3_CLK_APB)));
|
|
|
clk_dm(JH7110_UART3_CLK_CORE,
|
|
|
- starfive_clk_gate_divider(priv->sys,
|
|
|
- "u3_dw_uart_clk_core", "perh_root",
|
|
|
- SYS_OFFSET(JH7110_UART3_CLK_CORE), 8));
|
|
|
+ starfive_clk_gate_divider(priv->sys,
|
|
|
+ "u3_dw_uart_clk_core", "perh_root",
|
|
|
+ SYS_OFFSET(JH7110_UART3_CLK_CORE), 8));
|
|
|
|
|
|
/*UART4*/
|
|
|
clk_dm(JH7110_UART4_CLK_APB,
|
|
|
- starfive_clk_gate(priv->sys,
|
|
|
- "u4_dw_uart_clk_apb", "apb0",
|
|
|
- SYS_OFFSET(JH7110_UART4_CLK_APB)));
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u4_dw_uart_clk_apb", "apb0",
|
|
|
+ SYS_OFFSET(JH7110_UART4_CLK_APB)));
|
|
|
clk_dm(JH7110_UART4_CLK_CORE,
|
|
|
- starfive_clk_gate_divider(priv->sys,
|
|
|
- "u4_dw_uart_clk_core", "perh_root",
|
|
|
- SYS_OFFSET(JH7110_UART4_CLK_CORE), 8));
|
|
|
+ starfive_clk_gate_divider(priv->sys,
|
|
|
+ "u4_dw_uart_clk_core", "perh_root",
|
|
|
+ SYS_OFFSET(JH7110_UART4_CLK_CORE), 8));
|
|
|
|
|
|
/*UART5*/
|
|
|
clk_dm(JH7110_UART5_CLK_APB,
|
|
|
- starfive_clk_gate(priv->sys,
|
|
|
- "u5_dw_uart_clk_apb", "apb0",
|
|
|
- SYS_OFFSET(JH7110_UART5_CLK_APB)));
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u5_dw_uart_clk_apb", "apb0",
|
|
|
+ SYS_OFFSET(JH7110_UART5_CLK_APB)));
|
|
|
clk_dm(JH7110_UART5_CLK_CORE,
|
|
|
- starfive_clk_gate_divider(priv->sys,
|
|
|
- "u5_dw_uart_clk_core", "perh_root",
|
|
|
- SYS_OFFSET(JH7110_UART5_CLK_CORE), 8));
|
|
|
+ starfive_clk_gate_divider(priv->sys,
|
|
|
+ "u5_dw_uart_clk_core", "perh_root",
|
|
|
+ SYS_OFFSET(JH7110_UART5_CLK_CORE), 8));
|
|
|
|
|
|
clk_dm(JH7110_STG_APB,
|
|
|
- starfive_clk_fix_factor(priv->stg,
|
|
|
- "stg_apb", "apb_bus", 1, 1));
|
|
|
+ starfive_clk_fix_factor(priv->stg,
|
|
|
+ "stg_apb", "apb_bus", 1, 1));
|
|
|
/*USB*/
|
|
|
clk_dm(JH7110_USB0_CLK_USB_APB,
|
|
|
- starfive_clk_gate(priv->stg,
|
|
|
- "u0_cdn_usb_clk_usb_apb", "stg_apb",
|
|
|
- STG_OFFSET(JH7110_USB0_CLK_USB_APB)));
|
|
|
+ starfive_clk_gate(priv->stg,
|
|
|
+ "u0_cdn_usb_clk_usb_apb", "stg_apb",
|
|
|
+ STG_OFFSET(JH7110_USB0_CLK_USB_APB)));
|
|
|
clk_dm(JH7110_USB0_CLK_UTMI_APB,
|
|
|
- starfive_clk_gate(priv->stg,
|
|
|
- "u0_cdn_usb_clk_utmi_apb", "stg_apb",
|
|
|
- STG_OFFSET(JH7110_USB0_CLK_UTMI_APB)));
|
|
|
+ starfive_clk_gate(priv->stg,
|
|
|
+ "u0_cdn_usb_clk_utmi_apb", "stg_apb",
|
|
|
+ STG_OFFSET(JH7110_USB0_CLK_UTMI_APB)));
|
|
|
clk_dm(JH7110_USB0_CLK_AXI,
|
|
|
- starfive_clk_gate(priv->stg,
|
|
|
- "u0_cdn_usb_clk_axi", "stg_axiahb",
|
|
|
- STG_OFFSET(JH7110_USB0_CLK_AXI)));
|
|
|
+ starfive_clk_gate(priv->stg,
|
|
|
+ "u0_cdn_usb_clk_axi", "stg_axiahb",
|
|
|
+ STG_OFFSET(JH7110_USB0_CLK_AXI)));
|
|
|
clk_dm(JH7110_USB0_CLK_LPM,
|
|
|
- starfive_clk_gate_divider(priv->stg,
|
|
|
- "u0_cdn_usb_clk_lpm", "osc",
|
|
|
- STG_OFFSET(JH7110_USB0_CLK_LPM), 2));
|
|
|
+ starfive_clk_gate_divider(priv->stg,
|
|
|
+ "u0_cdn_usb_clk_lpm", "osc",
|
|
|
+ STG_OFFSET(JH7110_USB0_CLK_LPM), 2));
|
|
|
clk_dm(JH7110_USB0_CLK_STB,
|
|
|
- starfive_clk_gate_divider(priv->stg,
|
|
|
- "u0_cdn_usb_clk_stb", "osc",
|
|
|
- STG_OFFSET(JH7110_USB0_CLK_STB), 3));
|
|
|
+ starfive_clk_gate_divider(priv->stg,
|
|
|
+ "u0_cdn_usb_clk_stb", "osc",
|
|
|
+ STG_OFFSET(JH7110_USB0_CLK_STB), 3));
|
|
|
clk_dm(JH7110_USB0_CLK_APP_125,
|
|
|
- starfive_clk_gate(priv->stg,
|
|
|
- "u0_cdn_usb_clk_app_125", "usb_125m",
|
|
|
- STG_OFFSET(JH7110_USB0_CLK_APP_125)));
|
|
|
+ starfive_clk_gate(priv->stg,
|
|
|
+ "u0_cdn_usb_clk_app_125", "usb_125m",
|
|
|
+ STG_OFFSET(JH7110_USB0_CLK_APP_125)));
|
|
|
clk_dm(JH7110_USB0_REFCLK,
|
|
|
- starfive_clk_divider(priv->stg,
|
|
|
- "u0_cdn_usb_refclk", "osc",
|
|
|
- STG_OFFSET(JH7110_USB0_REFCLK), 2));
|
|
|
+ starfive_clk_divider(priv->stg,
|
|
|
+ "u0_cdn_usb_refclk", "osc",
|
|
|
+ STG_OFFSET(JH7110_USB0_REFCLK), 2));
|
|
|
|
|
|
/*GMAC1*/
|
|
|
clk_dm(JH7110_U0_GMAC5_CLK_AHB,
|
|
|
- starfive_clk_gate(priv->aon,
|
|
|
- "u0_dw_gmac5_axi64_clk_ahb", "aon_ahb",
|
|
|
- AON_OFFSET(JH7110_U0_GMAC5_CLK_AHB)));
|
|
|
+ starfive_clk_gate(priv->aon,
|
|
|
+ "u0_dw_gmac5_axi64_clk_ahb", "aon_ahb",
|
|
|
+ AON_OFFSET(JH7110_U0_GMAC5_CLK_AHB)));
|
|
|
clk_dm(JH7110_U0_GMAC5_CLK_AXI,
|
|
|
- starfive_clk_gate(priv->aon,
|
|
|
- "u0_dw_gmac5_axi64_clk_axi", "aon_ahb",
|
|
|
- AON_OFFSET(JH7110_U0_GMAC5_CLK_AXI)));
|
|
|
+ starfive_clk_gate(priv->aon,
|
|
|
+ "u0_dw_gmac5_axi64_clk_axi", "aon_ahb",
|
|
|
+ AON_OFFSET(JH7110_U0_GMAC5_CLK_AXI)));
|
|
|
clk_dm(JH7110_GMAC0_RMII_RTX,
|
|
|
- starfive_clk_divider(priv->aon,
|
|
|
- "gmac0_rmii_rtx", "gmac0_rmii_refin",
|
|
|
- AON_OFFSET(JH7110_GMAC0_RMII_RTX), 5));
|
|
|
+ starfive_clk_divider(priv->aon,
|
|
|
+ "gmac0_rmii_rtx", "gmac0_rmii_refin",
|
|
|
+ AON_OFFSET(JH7110_GMAC0_RMII_RTX), 5));
|
|
|
clk_dm(JH7110_U0_GMAC5_CLK_PTP,
|
|
|
- starfive_clk_fix_factor(priv->aon,
|
|
|
- "u0_dw_gmac5_axi64_clk_ptp",
|
|
|
- "gmac0_ptp", 1, 1));
|
|
|
+ starfive_clk_fix_factor(priv->aon,
|
|
|
+ "u0_dw_gmac5_axi64_clk_ptp",
|
|
|
+ "gmac0_ptp", 1, 1));
|
|
|
clk_dm(JH7110_U0_GMAC5_CLK_TX,
|
|
|
- starfive_clk_composite(priv->aon,
|
|
|
- "u0_dw_gmac5_axi64_clk_tx",
|
|
|
- u0_dw_gmac5_axi64_clk_tx_sels,
|
|
|
- ARRAY_SIZE(u0_dw_gmac5_axi64_clk_tx_sels),
|
|
|
- AON_OFFSET(JH7110_U0_GMAC5_CLK_TX), 1, 1, 0));
|
|
|
+ starfive_clk_composite(priv->aon,
|
|
|
+ "u0_dw_gmac5_axi64_clk_tx",
|
|
|
+ u0_dw_gmac5_axi64_clk_tx_sels,
|
|
|
+ ARRAY_SIZE(u0_dw_gmac5_axi64_clk_tx_sels),
|
|
|
+ AON_OFFSET(JH7110_U0_GMAC5_CLK_TX), 1, 1, 0));
|
|
|
/*otp*/
|
|
|
clk_dm(JH7110_OTPC_CLK_APB,
|
|
|
- starfive_clk_gate(priv->aon,
|
|
|
- "u0_otpc_clk_apb", "aon_apb",
|
|
|
- AON_OFFSET(JH7110_OTPC_CLK_APB)));
|
|
|
+ starfive_clk_gate(priv->aon,
|
|
|
+ "u0_otpc_clk_apb", "aon_apb",
|
|
|
+ AON_OFFSET(JH7110_OTPC_CLK_APB)));
|
|
|
+ /*vout*/
|
|
|
+ clk_dm(JH7110_VOUT_ROOT,
|
|
|
+ starfive_clk_fix_factor(priv->sys,
|
|
|
+ "vout_root", "pll2_out", 1, 1));
|
|
|
+ clk_dm(JH7110_AUDIO_ROOT,
|
|
|
+ starfive_clk_divider(priv->sys,
|
|
|
+ "audio_root", "pll2_out",
|
|
|
+ SYS_OFFSET(JH7110_AUDIO_ROOT), 5));
|
|
|
+ clk_dm(JH7110_VOUT_SRC,
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u0_dom_vout_top_clk_vout_src", "vout_root",
|
|
|
+ SYS_OFFSET(JH7110_VOUT_SRC)));
|
|
|
+ clk_dm(JH7110_VOUT_AXI,
|
|
|
+ starfive_clk_divider(priv->sys,
|
|
|
+ "vout_axi", "vout_root",
|
|
|
+ SYS_OFFSET(JH7110_VOUT_AXI), 3));
|
|
|
+ clk_dm(JH7110_VOUT_TOP_CLK_VOUT_AXI,
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u0_dom_vout_top_vout_axi", "vout_axi",
|
|
|
+ SYS_OFFSET(JH7110_VOUT_TOP_CLK_VOUT_AXI)));
|
|
|
+ clk_dm(JH7110_NOC_BUS_CLK_DISP_AXI,
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u0_sft7110_noc_bus_clk_disp_axi", "vout_axi",
|
|
|
+ SYS_OFFSET(JH7110_NOC_BUS_CLK_DISP_AXI)));
|
|
|
+ clk_dm(JH7110_VOUT_TOP_CLK_VOUT_AHB,
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u0_dom_vout_top_clk_vout_ahb", "ahb1",
|
|
|
+ SYS_OFFSET(JH7110_VOUT_TOP_CLK_VOUT_AHB)));
|
|
|
+ clk_dm(JH7110_MCLK_INNER,
|
|
|
+ starfive_clk_divider(priv->sys,
|
|
|
+ "mclk_inner", "audio_root",
|
|
|
+ SYS_OFFSET(JH7110_MCLK_INNER), 5));
|
|
|
+ clk_dm(JH7110_MCLK,
|
|
|
+ starfive_clk_mux(priv->sys, "mclk",
|
|
|
+ SYS_OFFSET(JH7110_MCLK), 1,
|
|
|
+ mclk_sels, ARRAY_SIZE(mclk_sels)));
|
|
|
+ clk_dm(JH7110_I2STX_4CH0_BCLK_MST,
|
|
|
+ starfive_clk_gate_divider(priv->sys,
|
|
|
+ "i2stx_4ch0_bclk_mst", "mclk",
|
|
|
+ SYS_OFFSET(JH7110_I2STX_4CH0_BCLK_MST), 5));
|
|
|
+ clk_dm(JH7110_I2STX0_4CHBCLK,
|
|
|
+ starfive_clk_mux(priv->sys, "u0_i2stx_4ch_bclk",
|
|
|
+ SYS_OFFSET(JH7110_I2STX0_4CHBCLK), 1,
|
|
|
+ u0_i2stx_4ch_bclk_sels, ARRAY_SIZE(u0_i2stx_4ch_bclk_sels)));
|
|
|
+ clk_dm(JH7110_VOUT_TOP_CLK_HDMITX0_BCLK,
|
|
|
+ starfive_clk_fix_factor(priv->sys,
|
|
|
+ "u0_dom_vout_top_clk_hdmitx0_bclk",
|
|
|
+ "u0_i2stx_4ch_bclk", 1, 1));
|
|
|
+ clk_dm(JH7110_VOUT_TOP_CLK_HDMITX0_MCLK,
|
|
|
+ starfive_clk_gate(priv->sys,
|
|
|
+ "u0_dom_vout_top_clk_hdmitx0_mclk", "mclk",
|
|
|
+ SYS_OFFSET(JH7110_VOUT_TOP_CLK_HDMITX0_MCLK)));
|
|
|
+ clk_dm(JH7110_VOUT_TOP_CLK_MIPIPHY_REF,
|
|
|
+ starfive_clk_divider(priv->sys,
|
|
|
+ "u0_dom_vout_top_clk_mipiphy_ref", "osc",
|
|
|
+ SYS_OFFSET(JH7110_MCLK_INNER), 2));
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int jh7110_clk_vout_init(struct udevice *dev)
|
|
|
+{
|
|
|
+ struct jh7110_clk_priv *priv = dev_get_priv(dev);
|
|
|
+
|
|
|
+ clk_dm(JH7110_DISP_ROOT,
|
|
|
+ starfive_clk_fix_factor(priv->vout,
|
|
|
+ "disp_root", "u0_dom_vout_top_clk_vout_src",
|
|
|
+ 1, 1));
|
|
|
+ clk_dm(JH7110_DISP_AXI,
|
|
|
+ starfive_clk_fix_factor(priv->vout,
|
|
|
+ "disp_axi", "u0_dom_vout_top_vout_axi",
|
|
|
+ 1, 1));
|
|
|
+ clk_dm(JH7110_DISP_AHB,
|
|
|
+ starfive_clk_fix_factor(priv->vout,
|
|
|
+ "disp_ahb", "u0_dom_vout_top_clk_vout_ahb",
|
|
|
+ 1, 1));
|
|
|
+ clk_dm(JH7110_HDMITX0_MCLK,
|
|
|
+ starfive_clk_fix_factor(priv->vout,
|
|
|
+ "hdmitx0_mclk", "u0_dom_vout_top_clk_hdmitx0_mclk",
|
|
|
+ 1, 1));
|
|
|
+ clk_dm(JH7110_HDMITX0_SCK,
|
|
|
+ starfive_clk_fix_factor(priv->vout,
|
|
|
+ "hdmitx0_sck", "u0_dom_vout_top_clk_hdmitx0_bclk",
|
|
|
+ 1, 1));
|
|
|
+ clk_dm(JH7110_APB,
|
|
|
+ starfive_clk_divider(priv->vout,
|
|
|
+ "apb", "disp_ahb",
|
|
|
+ VOUT_OFFSET(JH7110_APB), 5));
|
|
|
+ clk_dm(JH7110_U0_PCLK_MUX_FUNC_PCLK,
|
|
|
+ starfive_clk_fix_factor(priv->vout,
|
|
|
+ "u0_pclk_mux_func_pclk", "apb",
|
|
|
+ 1, 1));
|
|
|
+ clk_dm(JH7110_DISP_APB,
|
|
|
+ starfive_clk_fix_factor(priv->vout,
|
|
|
+ "disp_apb", "u0_pclk_mux_func_pclk",
|
|
|
+ 1, 1));
|
|
|
+ clk_dm(JH7110_TX_ESC,
|
|
|
+ starfive_clk_divider(priv->vout,
|
|
|
+ "tx_esc", "disp_ahb",
|
|
|
+ VOUT_OFFSET(JH7110_TX_ESC), 5));
|
|
|
+ clk_dm(JH7110_DC8200_PIX0,
|
|
|
+ starfive_clk_divider(priv->vout,
|
|
|
+ "dc8200_pix0", "disp_root",
|
|
|
+ VOUT_OFFSET(JH7110_DC8200_PIX0), 6));
|
|
|
+ clk_dm(JH7110_DSI_SYS,
|
|
|
+ starfive_clk_divider(priv->vout,
|
|
|
+ "dsi_sys", "disp_root",
|
|
|
+ VOUT_OFFSET(JH7110_DSI_SYS), 5));
|
|
|
+ clk_dm(JH7110_U0_DC8200_CLK_PIX0,
|
|
|
+ starfive_clk_composite(priv->vout,
|
|
|
+ "u0_dc8200_clk_pix0",
|
|
|
+ u0_dc8200_clk_pix_sels,
|
|
|
+ ARRAY_SIZE(u0_dc8200_clk_pix_sels),
|
|
|
+ VOUT_OFFSET(JH7110_U0_DC8200_CLK_PIX0), 1, 1, 0));
|
|
|
+ clk_dm(JH7110_U0_DC8200_CLK_PIX1,
|
|
|
+ starfive_clk_composite(priv->vout,
|
|
|
+ "u0_dc8200_clk_pix1",
|
|
|
+ u0_dc8200_clk_pix_sels,
|
|
|
+ ARRAY_SIZE(u0_dc8200_clk_pix_sels),
|
|
|
+ VOUT_OFFSET(JH7110_U0_DC8200_CLK_PIX1), 1, 1, 0));
|
|
|
+ clk_dm(JH7110_U0_DC8200_CLK_AXI,
|
|
|
+ starfive_clk_gate(priv->vout,
|
|
|
+ "u0_dc8200_clk_axi", "disp_axi",
|
|
|
+ VOUT_OFFSET(JH7110_U0_DC8200_CLK_AXI)));
|
|
|
+ clk_dm(JH7110_U0_DC8200_CLK_CORE,
|
|
|
+ starfive_clk_gate(priv->vout,
|
|
|
+ "u0_dc8200_clk_core", "disp_axi",
|
|
|
+ VOUT_OFFSET(JH7110_U0_DC8200_CLK_CORE)));
|
|
|
+ clk_dm(JH7110_U0_DC8200_CLK_AHB,
|
|
|
+ starfive_clk_gate(priv->vout,
|
|
|
+ "u0_dc8200_clk_ahb", "disp_ahb",
|
|
|
+ VOUT_OFFSET(JH7110_U0_DC8200_CLK_AHB)));
|
|
|
+ clk_dm(JH7110_U0_DC8200_CLK_PIX0_OUT,
|
|
|
+ starfive_clk_fix_factor(priv->vout,
|
|
|
+ "u0_dc8200_clk_pix0_out", "u0_dc8200_clk_pix0",
|
|
|
+ 1, 1));
|
|
|
+ clk_dm(JH7110_U0_DC8200_CLK_PIX1_OUT,
|
|
|
+ starfive_clk_fix_factor(priv->sys,
|
|
|
+ "u0_dc8200_clk_pix1_out", "u0_dc8200_clk_pix1",
|
|
|
+ 1, 1));
|
|
|
+ clk_dm(JH7110_DOM_VOUT_TOP_LCD_CLK,
|
|
|
+ starfive_clk_composite(priv->vout,
|
|
|
+ "dom_vout_top_lcd_clk",
|
|
|
+ dom_vout_top_lcd_clk_sels,
|
|
|
+ ARRAY_SIZE(dom_vout_top_lcd_clk_sels),
|
|
|
+ VOUT_OFFSET(JH7110_DOM_VOUT_TOP_LCD_CLK), 1, 1, 0));
|
|
|
+ clk_dm(JH7110_U0_MIPITX_DPHY_CLK_TXESC,
|
|
|
+ starfive_clk_gate(priv->vout,
|
|
|
+ "u0_mipitx_dphy_clk_txesc", "tx_esc",
|
|
|
+ VOUT_OFFSET(JH7110_U0_MIPITX_DPHY_CLK_TXESC)));
|
|
|
+ clk_dm(JH7110_U0_CDNS_DSITX_CLK_SYS,
|
|
|
+ starfive_clk_gate(priv->vout,
|
|
|
+ "u0_cdns_dsiTx_clk_sys", "dsi_sys",
|
|
|
+ VOUT_OFFSET(JH7110_U0_CDNS_DSITX_CLK_SYS)));
|
|
|
+ clk_dm(JH7110_U0_CDNS_DSITX_CLK_APB,
|
|
|
+ starfive_clk_gate(priv->vout,
|
|
|
+ "u0_cdns_dsiTx_clk_apb", "dsi_sys",
|
|
|
+ VOUT_OFFSET(JH7110_U0_CDNS_DSITX_CLK_APB)));
|
|
|
+ clk_dm(JH7110_U0_CDNS_DSITX_CLK_TXESC,
|
|
|
+ starfive_clk_gate(priv->vout,
|
|
|
+ "u0_cdns_dsiTx_clk_txesc", "tx_esc",
|
|
|
+ VOUT_OFFSET(JH7110_U0_CDNS_DSITX_CLK_TXESC)));
|
|
|
+ clk_dm(JH7110_U0_CDNS_DSITX_CLK_DPI,
|
|
|
+ starfive_clk_composite(priv->vout,
|
|
|
+ "u0_cdns_dsitx_clk_api",
|
|
|
+ u0_cdns_dsitx_clk_sels,
|
|
|
+ ARRAY_SIZE(u0_cdns_dsitx_clk_sels),
|
|
|
+ VOUT_OFFSET(JH7110_U0_CDNS_DSITX_CLK_DPI), 1, 1, 0));
|
|
|
+ clk_dm(JH7110_U0_HDMI_TX_CLK_SYS,
|
|
|
+ starfive_clk_gate(priv->vout,
|
|
|
+ "u0_hdmi_tx_clk_sys", "disp_apb",
|
|
|
+ VOUT_OFFSET(JH7110_U0_HDMI_TX_CLK_SYS)));
|
|
|
+ clk_dm(JH7110_U0_HDMI_TX_CLK_MCLK,
|
|
|
+ starfive_clk_gate(priv->vout,
|
|
|
+ "u0_hdmi_tx_clk_mclk", "hdmitx0_mclk",
|
|
|
+ VOUT_OFFSET(JH7110_U0_HDMI_TX_CLK_MCLK)));
|
|
|
+ clk_dm(JH7110_U0_HDMI_TX_CLK_BCLK,
|
|
|
+ starfive_clk_gate(priv->vout,
|
|
|
+ "u0_hdmi_tx_clk_bclk", "hdmitx0_sck",
|
|
|
+ VOUT_OFFSET(JH7110_U0_HDMI_TX_CLK_BCLK)));
|
|
|
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
+static int jh7110_clk_vout_probe(struct udevice *dev)
|
|
|
+{
|
|
|
+ struct jh7110_clk_priv *priv = dev_get_priv(dev);
|
|
|
+
|
|
|
+ priv->vout = (void __iomem *)dev_read_addr(dev);
|
|
|
+ if (!priv->vout)
|
|
|
+ return -EINVAL;
|
|
|
+
|
|
|
+ return jh7110_clk_vout_init(dev);
|
|
|
+}
|
|
|
+
|
|
|
static int jh7110_clk_probe(struct udevice *dev)
|
|
|
{
|
|
|
struct jh7110_clk_priv *priv = dev_get_priv(dev);
|
|
@@ -640,3 +861,17 @@ U_BOOT_DRIVER(jh7110_clk) = {
|
|
|
.priv_auto = sizeof(struct jh7110_clk_priv),
|
|
|
};
|
|
|
|
|
|
+static const struct udevice_id jh7110_clk_vout_of_match[] = {
|
|
|
+ { .compatible = "starfive,jh7110-clk-vout" },
|
|
|
+ { }
|
|
|
+};
|
|
|
+
|
|
|
+U_BOOT_DRIVER(jh7110_clk_vout) = {
|
|
|
+ .name = "jh7110_clk_vout",
|
|
|
+ .id = UCLASS_CLK,
|
|
|
+ .of_match = jh7110_clk_vout_of_match,
|
|
|
+ .probe = jh7110_clk_vout_probe,
|
|
|
+ .ops = &starfive_clk_ops,
|
|
|
+ .priv_auto = sizeof(struct jh7110_clk_priv),
|
|
|
+};
|
|
|
+
|