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+MediaTek Gen2 PCIe controller
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+
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+Required properties:
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+- compatible: Should contain one of the following strings:
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+ "mediatek,mt7623-pcie"
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+- device_type: Must be "pci"
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+- reg: Base addresses and lengths of the PCIe subsys and root ports.
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+- reg-names: Names of the above areas to use during resource lookup.
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+- #address-cells: Address representation for root ports (must be 3)
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+- #size-cells: Size representation for root ports (must be 2)
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+- clocks: Must contain an entry for each entry in clock-names.
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+- clock-names:
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+ Mandatory entries:
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+ - sys_ckN :transaction layer and data link layer clock
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+ Required entries for MT7623:
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+ - free_ck :for reference clock of PCIe subsys
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+ where N starting from 0 to one less than the number of root ports.
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+- phys: List of PHY specifiers (used by generic PHY framework).
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+- phy-names : Must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
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+ number of PHYs as specified in *phys* property.
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+- power-domains: A phandle and power domain specifier pair to the power domain
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+ which is responsible for collapsing and restoring power to the peripheral.
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+- bus-range: Range of bus numbers associated with this controller.
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+- ranges: Ranges for the PCI memory and I/O regions.
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+
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+Required properties for MT7623:
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+- #interrupt-cells: Size representation for interrupts (must be 1)
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+- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
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+ Please refer to the standard PCI bus binding document for a more detailed
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+ explanation.
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+- resets: Must contain an entry for each entry in reset-names.
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+- reset-names: Must be "pcie-rst0", "pcie-rst1", "pcie-rstN".. based on the
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+ number of root ports.
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+
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+In addition, the device tree node must have sub-nodes describing each
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+PCIe port interface, having the following mandatory properties:
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+
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+Required properties:
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+- device_type: Must be "pci"
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+- reg: Only the first four bytes are used to refer to the correct bus number
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+ and device number.
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+- #address-cells: Must be 3
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+- #size-cells: Must be 2
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+- #interrupt-cells: Must be 1
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+- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
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+ Please refer to the standard PCI bus binding document for a more detailed
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+ explanation.
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+- ranges: Sub-ranges distributed from the PCIe controller node. An empty
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+ property is sufficient.
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+
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+Examples for MT7623:
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+
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+ hifsys: syscon@1a000000 {
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+ compatible = "mediatek,mt7623-hifsys",
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+ "syscon";
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+ reg = <0x1a000000 0x1000>;
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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+
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+ pcie: pcie@1a140000 {
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+ compatible = "mediatek,mt7623-pcie";
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+ device_type = "pci";
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+ reg = <0x1a140000 0x1000>, /* PCIe shared registers */
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+ <0x1a142000 0x1000>, /* Port0 registers */
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+ <0x1a143000 0x1000>, /* Port1 registers */
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+ <0x1a144000 0x1000>; /* Port2 registers */
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+ reg-names = "subsys", "port0", "port1", "port2";
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0xf800 0 0 0>;
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+ interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
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+ <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
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+ <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
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+ clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
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+ <&hifsys CLK_HIFSYS_PCIE0>,
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+ <&hifsys CLK_HIFSYS_PCIE1>,
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+ <&hifsys CLK_HIFSYS_PCIE2>;
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+ clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
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+ resets = <&hifsys HIFSYS_PCIE0_RST>,
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+ <&hifsys HIFSYS_PCIE1_RST>,
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+ <&hifsys HIFSYS_PCIE2_RST>;
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+ reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
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+ phys = <&pcie0_phy PHY_TYPE_PCIE>, <&pcie1_phy PHY_TYPE_PCIE>,
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+ <&pcie2_phy PHY_TYPE_PCIE>;
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+ phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
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+ power-domains = <&scpsys MT7623_POWER_DOMAIN_HIF>;
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+ bus-range = <0x00 0xff>;
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+ ranges = <0x81000000 0 0x1a160000 0x1a160000 0 0x00010000 /* I/O space */
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+ 0x83000000 0 0x60000000 0x60000000 0 0x10000000>; /* memory space */
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+
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+ pcie@0,0 {
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+ reg = <0x0000 0 0 0 0>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 0>;
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+ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
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+ ranges;
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+ };
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+
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+ pcie@1,0 {
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+ reg = <0x0800 0 0 0 0>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 0>;
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+ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
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+ ranges;
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+ };
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+
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+ pcie@2,0 {
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+ reg = <0x1000 0 0 0 0>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 0>;
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+ interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
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+ ranges;
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+ };
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+ };
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