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riscv: dubhe: Set SYS_CACHELINE_SIZE 64

Signed-off-by: Wei Liang Lim <weiliang.lim@starfivetech.com>
Wei Liang Lim 7 months ago
parent
commit
7bf4461016
1 changed files with 3 additions and 0 deletions
  1. 3 0
      arch/riscv/cpu/dubhe/Kconfig

+ 3 - 0
arch/riscv/cpu/dubhe/Kconfig

@@ -16,3 +16,6 @@ config STARFIVE_DUBHE
 	imply SPL_OPENSBI
 	imply SPL_LOAD_FIT
 	imply MII
+
+config SYS_CACHELINE_SIZE
+	default 64