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@@ -4,7 +4,8 @@
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* Copyright (C) 2013 Imagination Technologies
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*/
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-#include <common.h>
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+#include <config.h>
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+#include <fdt_support.h>
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#include <ide.h>
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#include <init.h>
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#include <net.h>
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@@ -24,6 +25,9 @@
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DECLARE_GLOBAL_DATA_PTR;
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+#define MALTA_GT_PATH "/pci0@1be00000"
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+#define MALTA_MSC_PATH "/pci0@1bd00000"
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+
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enum core_card {
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CORE_UNKNOWN,
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CORE_LV,
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@@ -120,10 +124,12 @@ int checkboard(void)
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return 0;
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}
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+#if !IS_ENABLED(CONFIG_DM_ETH)
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int board_eth_init(struct bd_info *bis)
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{
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return pci_eth_init(bis);
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}
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+#endif
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void _machine_restart(void)
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{
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@@ -167,6 +173,77 @@ int misc_init_r(void)
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return 0;
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}
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+#if IS_ENABLED(CONFIG_OF_BOARD_FIXUP)
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+/*
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+ * TODO: currently doesn't work because rw_fdt_blob points to a
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+ * NOR flash address. This needs some changes in board_init_f.
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+ */
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+int board_fix_fdt(void *rw_fdt_blob)
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+{
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+ int node = -1;
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+
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+ switch (malta_sys_con()) {
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+ case SYSCON_GT64120:
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+ node = fdt_path_offset(rw_fdt_blob, MALTA_GT_PATH);
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+ break;
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+ default:
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+ case SYSCON_MSC01:
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+ node = fdt_path_offset(rw_fdt_blob, MALTA_MSC_PATH);
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+ break;
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+ }
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+
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+ return fdt_status_okay(rw_fdt_blob, node);
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+}
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+#endif
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+
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+#if IS_ENABLED(CONFIG_DM_PCI)
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+int board_early_init_r(void)
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+{
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+ struct udevice *dev;
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+ int ret;
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+
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+ pci_init();
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+
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+ ret = dm_pci_find_device(PCI_VENDOR_ID_INTEL,
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+ PCI_DEVICE_ID_INTEL_82371AB_0, 0, &dev);
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+ if (ret)
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+ panic("Failed to find PIIX4 PCI bridge\n");
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+
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+ /* setup PCI interrupt routing */
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+ dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCA, 10);
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+ dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCB, 10);
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+ dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCC, 11);
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+ dm_pci_write_config8(dev, PCI_CFG_PIIX4_PIRQRCD, 11);
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+
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+ /* mux SERIRQ onto SERIRQ pin */
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+ dm_pci_clrset_config32(dev, PCI_CFG_PIIX4_GENCFG, 0,
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+ PCI_CFG_PIIX4_GENCFG_SERIRQ);
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+
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+ /* enable SERIRQ - Linux currently depends upon this */
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+ dm_pci_clrset_config8(dev, PCI_CFG_PIIX4_SERIRQC, 0,
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+ PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT);
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+
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+ ret = dm_pci_find_device(PCI_VENDOR_ID_INTEL,
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+ PCI_DEVICE_ID_INTEL_82371AB, 0, &dev);
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+ if (ret)
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+ panic("Failed to find PIIX4 IDE controller\n");
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+
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+ /* enable bus master & IO access */
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+ dm_pci_clrset_config32(dev, PCI_COMMAND, 0,
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+ PCI_COMMAND_MASTER | PCI_COMMAND_IO);
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+
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+ /* set latency */
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+ dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
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+
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+ /* enable IDE/ATA */
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+ dm_pci_write_config32(dev, PCI_CFG_PIIX4_IDETIM_PRI,
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+ PCI_CFG_PIIX4_IDETIM_IDE);
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+ dm_pci_write_config32(dev, PCI_CFG_PIIX4_IDETIM_SEC,
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+ PCI_CFG_PIIX4_IDETIM_IDE);
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+
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+ return 0;
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+}
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+#else
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void pci_init_board(void)
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{
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pci_dev_t bdf;
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@@ -231,3 +308,4 @@ void pci_init_board(void)
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pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC,
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PCI_CFG_PIIX4_IDETIM_IDE);
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}
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+#endif
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