The frequency of cclk_in is limited to 50M, so that it does not do internal part frequency and goes by-pass mode. And delete syscon node. Signed-off-by: William Qiu <william.qiu@starfivetech.com>
@@ -246,6 +246,8 @@
};
&sdio0 {
+ assigned-clocks = <&clkgen JH7110_SDIO0_CLK_SDCARD>;
+ assigned-clock-rates = <50000000>;
fifo-depth = <32>;
bus-width = <4>;
status = "okay";