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riscv: dts: starfive: limit cclk_in frequency

The frequency of cclk_in is limited to 50M, so that it does not do internal
part frequency and goes by-pass mode. And delete syscon node.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
William Qiu 10 months ago
parent
commit
7818499b71
1 changed files with 2 additions and 0 deletions
  1. 2 0
      arch/riscv/dts/starfive_evb.dts

+ 2 - 0
arch/riscv/dts/starfive_evb.dts

@@ -246,6 +246,8 @@
 };
 
 &sdio0 {
+	assigned-clocks = <&clkgen JH7110_SDIO0_CLK_SDCARD>;
+	assigned-clock-rates = <50000000>;
 	fifo-depth = <32>;
 	bus-width = <4>;
 	status = "okay";