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@@ -80,54 +80,6 @@ static iomux_v3_cfg_t const enet_pads[] = {
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IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
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};
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-#ifdef CONFIG_CMD_NAND
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-static iomux_v3_cfg_t const nfc_pads[] = {
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- IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
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- IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
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- IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
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- IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
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- IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
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- IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
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- IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
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- IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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- IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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- IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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- IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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- IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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- IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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- IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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- IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
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-};
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-
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-static void setup_gpmi_nand(void)
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-{
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- struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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-
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- /* config gpmi nand iomux */
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- SETUP_IOMUX_PADS(nfc_pads);
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-
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- /* config gpmi and bch clock to 100 MHz */
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- clrsetbits_le32(&mxc_ccm->cs2cdr,
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- MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
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- MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
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- MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
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- MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
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- MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
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- MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
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-
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- /* enable gpmi and bch clock gating */
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- setbits_le32(&mxc_ccm->CCGR4,
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- MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
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- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
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- MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
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- MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
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- MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
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-
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- /* enable apbh clock gating */
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- setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
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-}
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-#endif
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-
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static void setup_iomux_enet(int gpio)
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{
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SETUP_IOMUX_PADS(enet_pads);
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@@ -639,10 +591,6 @@ int board_init(void)
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setup_ventana_i2c(0);
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board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
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-#ifdef CONFIG_CMD_NAND
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- if (gpio_cfg[board_type].nand)
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- setup_gpmi_nand();
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-#endif
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#ifdef CONFIG_MXC_SPI
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setup_spi();
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#endif
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