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@@ -0,0 +1,411 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Renesas RCar Gen3 PCIEC driver
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+ *
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+ * Copyright (C) 2018-2019 Marek Vasut <marek.vasut@gmail.com>
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+ *
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+ * Based on Linux PCIe driver for Renesas R-Car SoCs
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+ * Copyright (C) 2014 Renesas Electronics Europe Ltd
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+ *
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+ * Based on:
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+ * arch/sh/drivers/pci/pcie-sh7786.c
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+ * arch/sh/drivers/pci/ops-sh7786.c
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+ * Copyright (C) 2009 - 2011 Paul Mundt
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+ *
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+ * Author: Phil Edworthy <phil.edworthy@renesas.com>
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+ */
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+
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+#include <common.h>
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+#include <asm/io.h>
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+#include <clk.h>
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+#include <dm.h>
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+#include <errno.h>
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+#include <pci.h>
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+#include <wait_bit.h>
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+
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+#define PCIECAR 0x000010
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+#define PCIECCTLR 0x000018
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+#define CONFIG_SEND_ENABLE BIT(31)
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+#define TYPE0 (0 << 8)
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+#define TYPE1 BIT(8)
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+#define PCIECDR 0x000020
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+#define PCIEMSR 0x000028
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+#define PCIEINTXR 0x000400
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+#define PCIEPHYSR 0x0007f0
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+#define PHYRDY BIT(0)
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+#define PCIEMSITXR 0x000840
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+
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+/* Transfer control */
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+#define PCIETCTLR 0x02000
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+#define CFINIT 1
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+#define PCIETSTR 0x02004
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+#define DATA_LINK_ACTIVE 1
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+#define PCIEERRFR 0x02020
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+#define UNSUPPORTED_REQUEST BIT(4)
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+#define PCIEMSIFR 0x02044
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+#define PCIEMSIALR 0x02048
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+#define MSIFE 1
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+#define PCIEMSIAUR 0x0204c
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+#define PCIEMSIIER 0x02050
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+
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+/* root port address */
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+#define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
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+
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+/* local address reg & mask */
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+#define PCIELAR(x) (0x02200 + ((x) * 0x20))
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+#define PCIELAMR(x) (0x02208 + ((x) * 0x20))
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+#define LAM_PREFETCH BIT(3)
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+#define LAM_64BIT BIT(2)
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+#define LAR_ENABLE BIT(1)
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+
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+/* PCIe address reg & mask */
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+#define PCIEPALR(x) (0x03400 + ((x) * 0x20))
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+#define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
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+#define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
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+#define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
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+#define PAR_ENABLE BIT(31)
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+#define IO_SPACE BIT(8)
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+
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+/* Configuration */
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+#define PCICONF(x) (0x010000 + ((x) * 0x4))
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+#define PMCAP(x) (0x010040 + ((x) * 0x4))
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+#define EXPCAP(x) (0x010070 + ((x) * 0x4))
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+#define VCCAP(x) (0x010100 + ((x) * 0x4))
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+
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+/* link layer */
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+#define IDSETR1 0x011004
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+#define TLCTLR 0x011048
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+#define MACSR 0x011054
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+#define SPCHGFIN BIT(4)
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+#define SPCHGFAIL BIT(6)
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+#define SPCHGSUC BIT(7)
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+#define LINK_SPEED (0xf << 16)
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+#define LINK_SPEED_2_5GTS (1 << 16)
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+#define LINK_SPEED_5_0GTS (2 << 16)
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+#define MACCTLR 0x011058
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+#define SPEED_CHANGE BIT(24)
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+#define SCRAMBLE_DISABLE BIT(27)
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+#define MACS2R 0x011078
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+#define MACCGSPSETR 0x011084
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+#define SPCNGRSN BIT(31)
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+
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+/* R-Car H1 PHY */
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+#define H1_PCIEPHYADRR 0x04000c
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+#define WRITE_CMD BIT(16)
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+#define PHY_ACK BIT(24)
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+#define RATE_POS 12
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+#define LANE_POS 8
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+#define ADR_POS 0
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+#define H1_PCIEPHYDOUTR 0x040014
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+
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+/* R-Car Gen2 PHY */
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+#define GEN2_PCIEPHYADDR 0x780
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+#define GEN2_PCIEPHYDATA 0x784
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+#define GEN2_PCIEPHYCTRL 0x78c
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+
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+#define INT_PCI_MSI_NR 32
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+
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+#define RCONF(x) (PCICONF(0) + (x))
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+#define RPMCAP(x) (PMCAP(0) + (x))
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+#define REXPCAP(x) (EXPCAP(0) + (x))
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+#define RVCCAP(x) (VCCAP(0) + (x))
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+
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+#define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
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+#define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
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+#define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
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+
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+#define RCAR_PCI_MAX_RESOURCES 4
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+#define MAX_NR_INBOUND_MAPS 6
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+
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+#define PCI_EXP_FLAGS 2 /* Capabilities register */
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+#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
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+#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
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+#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
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+#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
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+#define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
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+#define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */
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+
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+enum {
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+ RCAR_PCI_ACCESS_READ,
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+ RCAR_PCI_ACCESS_WRITE,
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+};
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+
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+struct rcar_gen3_pcie_priv {
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+ fdt_addr_t regs;
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+};
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+
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+static void rcar_rmw32(struct udevice *dev, int where, u32 mask, u32 data)
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+{
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+ struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
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+ int shift = 8 * (where & 3);
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+
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+ clrsetbits_le32(priv->regs + (where & ~3),
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+ mask << shift, data << shift);
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+}
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+
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+static u32 rcar_read_conf(struct udevice *dev, int where)
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+{
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+ struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
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+ int shift = 8 * (where & 3);
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+
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+ return readl(priv->regs + (where & ~3)) >> shift;
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+}
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+
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+static int rcar_pcie_config_access(struct udevice *udev,
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+ unsigned char access_type,
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+ pci_dev_t bdf, int where, ulong *data)
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+{
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+ struct rcar_gen3_pcie_priv *priv = dev_get_platdata(udev);
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+ u32 reg = where & ~3;
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+
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+ /* Clear errors */
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+ clrbits_le32(priv->regs + PCIEERRFR, 0);
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+
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+ /* Set the PIO address */
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+ writel((bdf << 8) | reg, priv->regs + PCIECAR);
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+
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+ /* Enable the configuration access */
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+ if (!PCI_BUS(bdf))
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+ writel(CONFIG_SEND_ENABLE | TYPE0, priv->regs + PCIECCTLR);
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+ else
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+ writel(CONFIG_SEND_ENABLE | TYPE1, priv->regs + PCIECCTLR);
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+
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+ /* Check for errors */
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+ if (readl(priv->regs + PCIEERRFR) & UNSUPPORTED_REQUEST)
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+ return -ENODEV;
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+
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+ /* Check for master and target aborts */
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+ if (rcar_read_conf(udev, RCONF(PCI_STATUS)) &
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+ (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
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+ return -ENODEV;
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+
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+ if (access_type == RCAR_PCI_ACCESS_READ)
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+ *data = readl(priv->regs + PCIECDR);
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+ else
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+ writel(*data, priv->regs + PCIECDR);
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+
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+ /* Disable the configuration access */
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+ writel(0, priv->regs + PCIECCTLR);
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+
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+ return 0;
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+}
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+
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+static int rcar_gen3_pcie_addr_valid(pci_dev_t d, uint where)
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+{
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+ u32 slot;
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+
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+ if (PCI_FUNC(d))
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+ return -EINVAL;
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+
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+ slot = PCI_DEV(d);
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+ if (slot != 1)
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+ return -EINVAL;
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+
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+ return 0;
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+}
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+
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+static int rcar_gen3_pcie_read_config(struct udevice *dev, pci_dev_t bdf,
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+ uint where, ulong *val,
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+ enum pci_size_t size)
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+{
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+ ulong reg;
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+ int ret;
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+
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+ ret = rcar_gen3_pcie_addr_valid(bdf, where);
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+ if (ret) {
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+ *val = pci_get_ff(size);
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+ return 0;
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+ }
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+
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+ ret = rcar_pcie_config_access(dev, RCAR_PCI_ACCESS_READ,
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+ bdf, where, ®);
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+ if (ret != 0)
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+ reg = 0xffffffffUL;
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+
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+ *val = pci_conv_32_to_size(reg, where, size);
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+
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+ return ret;
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+}
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+
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+static int rcar_gen3_pcie_write_config(struct udevice *dev, pci_dev_t bdf,
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+ uint where, ulong val,
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+ enum pci_size_t size)
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+{
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+ ulong data;
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+ int ret;
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+
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+ ret = rcar_gen3_pcie_addr_valid(bdf, where);
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+ if (ret)
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+ return ret;
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+
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+ data = pci_conv_32_to_size(val, where, size);
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+
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+ ret = rcar_pcie_config_access(dev, RCAR_PCI_ACCESS_WRITE,
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+ bdf, where, &data);
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+
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+ return ret;
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+}
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+
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+static int rcar_gen3_pcie_wait_for_phyrdy(struct udevice *dev)
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+{
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+ struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
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+
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+ return wait_for_bit_le32((void *)priv->regs + PCIEPHYSR, PHYRDY,
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+ true, 50, false);
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+}
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+
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+static int rcar_gen3_pcie_wait_for_dl(struct udevice *dev)
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+{
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+ struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
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+
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+ return wait_for_bit_le32((void *)priv->regs + PCIETSTR,
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+ DATA_LINK_ACTIVE, true, 50, false);
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+}
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+
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+static int rcar_gen3_pcie_hw_init(struct udevice *dev)
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+{
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+ struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
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+ int ret;
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+
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+ /* Begin initialization */
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+ writel(0, priv->regs + PCIETCTLR);
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+
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+ /* Set mode */
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+ writel(1, priv->regs + PCIEMSR);
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+
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+ ret = rcar_gen3_pcie_wait_for_phyrdy(dev);
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+ if (ret)
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+ return ret;
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+
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+ /*
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+ * Initial header for port config space is type 1, set the device
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+ * class to match. Hardware takes care of propagating the IDSETR
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+ * settings, so there is no need to bother with a quirk.
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+ */
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+ writel(PCI_CLASS_BRIDGE_PCI << 16, priv->regs + IDSETR1);
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+
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+ /*
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+ * Setup Secondary Bus Number & Subordinate Bus Number, even though
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+ * they aren't used, to avoid bridge being detected as broken.
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+ */
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+ rcar_rmw32(dev, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
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+ rcar_rmw32(dev, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
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+
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+ /* Initialize default capabilities. */
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+ rcar_rmw32(dev, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
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+ rcar_rmw32(dev, REXPCAP(PCI_EXP_FLAGS),
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+ PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
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+ rcar_rmw32(dev, RCONF(PCI_HEADER_TYPE), 0x7f,
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+ PCI_HEADER_TYPE_BRIDGE);
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+
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+ /* Enable data link layer active state reporting */
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+ rcar_rmw32(dev, REXPCAP(PCI_EXP_LNKCAP),
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+ PCI_EXP_LNKCAP_DLLLARC, PCI_EXP_LNKCAP_DLLLARC);
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+
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+ /* Write out the physical slot number = 0 */
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+ rcar_rmw32(dev, REXPCAP(PCI_EXP_SLTCAP),
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+ PCI_EXP_SLTCAP_PSN, 0);
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+
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+ /* Set the completion timer timeout to the maximum 50ms. */
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+ rcar_rmw32(dev, TLCTLR + 1, 0x3f, 50);
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+
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+ /* Terminate list of capabilities (Next Capability Offset=0) */
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+ rcar_rmw32(dev, RVCCAP(0), 0xfff00000, 0);
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+
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+ /* Finish initialization - establish a PCI Express link */
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+ writel(CFINIT, priv->regs + PCIETCTLR);
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+
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+ return rcar_gen3_pcie_wait_for_dl(dev);
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+}
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+
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+static int rcar_gen3_pcie_probe(struct udevice *dev)
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+{
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+ struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
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+ struct pci_controller *hose = dev_get_uclass_priv(dev);
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+ struct clk pci_clk;
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+ u32 mask;
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+ int i, cnt, ret;
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+
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+ ret = clk_get_by_index(dev, 0, &pci_clk);
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+ if (ret)
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+ return ret;
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+
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+ ret = clk_enable(&pci_clk);
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+ if (ret)
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+ return ret;
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+
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+ for (i = 0; i < hose->region_count; i++) {
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+ if (hose->regions[i].flags != PCI_REGION_SYS_MEMORY)
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+ continue;
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+
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+ if (hose->regions[i].phys_start == 0)
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+ continue;
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+
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+ mask = (hose->regions[i].size - 1) & ~0xf;
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+ mask |= LAR_ENABLE;
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+ writel(hose->regions[i].phys_start, priv->regs + PCIEPRAR(0));
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+ writel(hose->regions[i].phys_start, priv->regs + PCIELAR(0));
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+ writel(mask, priv->regs + PCIELAMR(0));
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+ break;
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+ }
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+
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+ writel(0, priv->regs + PCIEPRAR(4));
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+ writel(0, priv->regs + PCIELAR(4));
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+ writel(0, priv->regs + PCIELAMR(4));
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+
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+ ret = rcar_gen3_pcie_hw_init(dev);
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+ if (ret)
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+ return ret;
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+
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+ for (i = 0, cnt = 0; i < hose->region_count; i++) {
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+ if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY)
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+ continue;
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+
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+ writel(0, priv->regs + PCIEPTCTLR(cnt));
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+ writel((hose->regions[i].size - 1) & ~0x7f,
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+ priv->regs + PCIEPAMR(cnt));
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+ writel(upper_32_bits(hose->regions[i].phys_start),
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+ priv->regs + PCIEPAUR(cnt));
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+ writel(lower_32_bits(hose->regions[i].phys_start),
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+ priv->regs + PCIEPALR(cnt));
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+ mask = PAR_ENABLE;
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+ if (hose->regions[i].flags == PCI_REGION_IO)
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+ mask |= IO_SPACE;
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+ writel(mask, priv->regs + PCIEPTCTLR(cnt));
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+
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+ cnt++;
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+ }
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+
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+ return 0;
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+}
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+
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+static int rcar_gen3_pcie_ofdata_to_platdata(struct udevice *dev)
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|
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+{
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|
|
+ struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
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|
|
+
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|
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+ priv->regs = devfdt_get_addr_index(dev, 0);
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|
|
+ if (!priv->regs)
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|
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+ return -EINVAL;
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+
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|
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+ return 0;
|
|
|
+}
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|
|
+
|
|
|
+static const struct dm_pci_ops rcar_gen3_pcie_ops = {
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|
|
+ .read_config = rcar_gen3_pcie_read_config,
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|
|
+ .write_config = rcar_gen3_pcie_write_config,
|
|
|
+};
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|
|
+
|
|
|
+static const struct udevice_id rcar_gen3_pcie_ids[] = {
|
|
|
+ { .compatible = "renesas,pcie-rcar-gen3" },
|
|
|
+ { }
|
|
|
+};
|
|
|
+
|
|
|
+U_BOOT_DRIVER(rcar_gen3_pcie) = {
|
|
|
+ .name = "rcar_gen3_pcie",
|
|
|
+ .id = UCLASS_PCI,
|
|
|
+ .of_match = rcar_gen3_pcie_ids,
|
|
|
+ .ops = &rcar_gen3_pcie_ops,
|
|
|
+ .probe = rcar_gen3_pcie_probe,
|
|
|
+ .ofdata_to_platdata = rcar_gen3_pcie_ofdata_to_platdata,
|
|
|
+ .platdata_auto_alloc_size = sizeof(struct rcar_gen3_pcie_priv),
|
|
|
+};
|