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clk:starfive-jh7110: Update pll0/pll1/pll2 clk

Add JH7110_GMAC0_GTXC clk register and remove pll0/pll1/pll2 clk define
from clk-jh7110.c  to jh7110_clk.dts

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
yanhong.wang 2 years ago
parent
commit
76c3fe3888
3 changed files with 29 additions and 6 deletions
  1. 4 2
      arch/riscv/dts/jh7110.dtsi
  2. 18 1
      arch/riscv/dts/jh7110_clk.dtsi
  3. 7 3
      drivers/clk/starfive/clk-jh7110.c

+ 4 - 2
arch/riscv/dts/jh7110.dtsi

@@ -785,12 +785,14 @@
 				"tx",
 				"ptp_ref",
 				"stmmaceth",
-				"pclk";
+				"pclk",
+				"gtxc";
 			clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
 				 <&clkgen JH7110_U0_GMAC5_CLK_TX>,
 				 <&clkgen JH7110_GMAC0_PTP>,
 				 <&clkgen JH7110_U0_GMAC5_CLK_AHB>,
-				 <&clkgen JH7110_U0_GMAC5_CLK_AXI>;
+				 <&clkgen JH7110_U0_GMAC5_CLK_AXI>,
+				 <&clkgen JH7110_GMAC0_GTXC>;
 			resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
 				 <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
 			reset-names = "ahb", "stmmaceth";

+ 18 - 1
arch/riscv/dts/jh7110_clk.dtsi

@@ -112,6 +112,23 @@
 		#clock-cells = <0>;
 		clock-frequency = <297000000>;
 	};
-
 	/* external clocks end */
+
+	pll0_out: pll0_out {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1000000000>;
+	};
+
+	pll1_out: pll1_out {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1066000000>;
+	};
+
+	pll2_out: pll2_out {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <1228800000>;
+	};
 };

+ 7 - 3
drivers/clk/starfive/clk-jh7110.c

@@ -49,7 +49,7 @@ static const char *bus_root_sels[2] = {
 
 static const char *qspi_ref_sels[2] = {
 	[0] = "osc",
-	[1] = "clk_qspi_ref_src",
+	[1] = "u0_cdns_qspi_ref_src",
 };
 
 static const char *gmac5_tx_sels[2] = {
@@ -303,7 +303,7 @@ static struct clk *starfive_clk_gate_divider(void __iomem *reg,
 static int jh7110_clk_init(struct udevice *dev)
 {
 	struct jh7110_clk_priv *priv = dev_get_priv(dev);
-
+#if 0
 	clk_dm(JH7110_PLL0_OUT,
 		starfive_clk_fix_factor(priv->sys,
 			"pll0_out", "osc", 52, 1));
@@ -313,7 +313,7 @@ static int jh7110_clk_init(struct udevice *dev)
 	clk_dm(JH7110_PLL2_OUT,
 		starfive_clk_fix_factor(priv->sys,
 			"pll2_out", "osc", 51, 1));
-
+#endif
 	/*root*/
 	clk_dm(JH7110_CPU_ROOT,
 		starfive_clk_mux(priv->sys, "cpu_root",
@@ -474,6 +474,10 @@ static int jh7110_clk_init(struct udevice *dev)
 	clk_dm(JH7110_GMAC0_PTP,
 		starfive_clk_gate_divider(priv->sys, "gmac0_ptp",
 			"gmac_src", SYS_OFFSET(JH7110_GMAC0_PTP), 5));
+	clk_dm(JH7110_GMAC0_GTXC,
+		starfive_clk_gate(priv->sys,
+			"gmac0_gtxc", "gmac0_gtxclk",
+			SYS_OFFSET(JH7110_GMAC0_GTXC)));
 	/*UART0*/
 	clk_dm(JH7110_UART0_CLK_APB,
 		starfive_clk_gate(priv->sys,