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@@ -49,7 +49,7 @@ static const char *bus_root_sels[2] = {
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static const char *qspi_ref_sels[2] = {
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[0] = "osc",
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- [1] = "clk_qspi_ref_src",
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+ [1] = "u0_cdns_qspi_ref_src",
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};
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static const char *gmac5_tx_sels[2] = {
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@@ -303,7 +303,7 @@ static struct clk *starfive_clk_gate_divider(void __iomem *reg,
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static int jh7110_clk_init(struct udevice *dev)
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{
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struct jh7110_clk_priv *priv = dev_get_priv(dev);
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-
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+#if 0
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clk_dm(JH7110_PLL0_OUT,
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starfive_clk_fix_factor(priv->sys,
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"pll0_out", "osc", 52, 1));
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@@ -313,7 +313,7 @@ static int jh7110_clk_init(struct udevice *dev)
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clk_dm(JH7110_PLL2_OUT,
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starfive_clk_fix_factor(priv->sys,
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"pll2_out", "osc", 51, 1));
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-
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+#endif
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/*root*/
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clk_dm(JH7110_CPU_ROOT,
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starfive_clk_mux(priv->sys, "cpu_root",
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@@ -474,6 +474,10 @@ static int jh7110_clk_init(struct udevice *dev)
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clk_dm(JH7110_GMAC0_PTP,
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starfive_clk_gate_divider(priv->sys, "gmac0_ptp",
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"gmac_src", SYS_OFFSET(JH7110_GMAC0_PTP), 5));
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+ clk_dm(JH7110_GMAC0_GTXC,
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+ starfive_clk_gate(priv->sys,
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+ "gmac0_gtxc", "gmac0_gtxclk",
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+ SYS_OFFSET(JH7110_GMAC0_GTXC)));
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/*UART0*/
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clk_dm(JH7110_UART0_CLK_APB,
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starfive_clk_gate(priv->sys,
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