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+I2C Edge Conditions:
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+====================
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+
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+ I2C devices may be left in a write state if a read was occuring
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+ and the CPU was reset. This may result in EEPROM data corruption.
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+
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+ The edge condition is as follows:
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+ 1) A read operation begins.
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+ 2) I2C controller issues a start command.
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+ 3) The I2C writes the device address.
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+ 4) The CPU is reset at this point.
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+
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+ Once the CPU reinitializes and the read is tried again:
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+ 1) The I2C controller issues a start command.
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+ 2) The I2C controller writes the device address.
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+ 3) The I2C controller writes the offset.
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+
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+ The EEPROM sees:
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+ 1) START
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+ 2) device address
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+ 3) START "this start is ignored by most EEPROMs"
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+ 4) device address "EEPROM interprets this as offset"
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+ 5) Offset in device, "EEPROM interprets this as data to write"
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+
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+ The device will interpret this sequence as a WRITE command and
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+ write rubbish into itself, i.e. the "offset" will be interpreted
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+ as data to be written in location "device address".
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+
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+Notes
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+-----
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+!!!THIS IS AN UNDOCUMENTED I2C BUS BUG, NOT A IBM 4xx BUG!!!
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+
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+This reset edge condition could possibly be present in every I2C
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+controller and device available. We should probably have a bus reset
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+function for all our target CPUs.
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+
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+Many thanks to Bill Hunter for finding this serious BUG.
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+email to: <williamhunter@attbi.com>
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+
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+Erik Theisen <etheisen@mindspring.com>
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+Tue, 5 Mar 2002 23:02:19 -0500 (Wed 05:02 MET)
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