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@@ -0,0 +1,157 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Rockchip PCIE3.0 phy driver
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+ *
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+ * Copyright (C) 2021 Rockchip Electronics Co., Ltd.
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+ */
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+
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+#include <common.h>
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+#include <clk.h>
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+#include <dm.h>
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+#include <generic-phy.h>
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+#include <regmap.h>
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+#include <reset-uclass.h>
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+#include <syscon.h>
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+#include <asm/io.h>
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+#include <dm/device_compat.h>
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+#include <dm/lists.h>
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+
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+#define GRF_PCIE30PHY_CON1 0x4
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+#define GRF_PCIE30PHY_CON6 0x18
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+#define GRF_PCIE30PHY_CON9 0x24
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+
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+/**
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+ * struct rockchip_p3phy_priv - RK DW PCIe PHY state
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+ *
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+ * @mmio: The base address of PHY internal registers
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+ * @phy_grf: The regmap for controlling pipe signal
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+ * @p30phy: The reset signal for PHY
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+ * @ref_clk_m: The reference clock of M for PHY
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+ * @ref_clk_n: The reference clock of N for PHY
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+ * @pclk: The clock for accessing PHY blocks
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+ */
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+struct rockchip_p3phy_priv {
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+ void __iomem *mmio;
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+ struct regmap *phy_grf;
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+ struct reset_ctl p30phy;
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+ struct clk ref_clk_m;
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+ struct clk ref_clk_n;
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+ struct clk pclk;
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+};
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+
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+static int rochchip_p3phy_init(struct phy *phy)
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+{
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+ struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
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+ int ret;
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+
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+ ret = clk_enable(&priv->ref_clk_m);
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+ if (ret < 0 && ret != -ENOSYS)
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+ return ret;
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+
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+ ret = clk_enable(&priv->ref_clk_n);
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+ if (ret < 0 && ret != -ENOSYS)
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+ goto err_ref;
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+
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+ ret = clk_enable(&priv->pclk);
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+ if (ret < 0 && ret != -ENOSYS)
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+ goto err_pclk;
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+
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+ reset_assert(&priv->p30phy);
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+ udelay(1);
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+
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+ /* Deassert PCIe PMA output clamp mode */
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+ regmap_write(priv->phy_grf, GRF_PCIE30PHY_CON9,
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+ (0x1 << 15) | (0x1 << 31));
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+
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+ reset_deassert(&priv->p30phy);
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+ udelay(1);
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+
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+ return 0;
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+err_pclk:
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+ clk_disable(&priv->ref_clk_n);
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+err_ref:
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+ clk_disable(&priv->ref_clk_m);
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+
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+ return ret;
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+}
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+
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+static int rochchip_p3phy_exit(struct phy *phy)
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+{
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+ struct rockchip_p3phy_priv *priv = dev_get_priv(phy->dev);
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+
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+ clk_disable(&priv->ref_clk_m);
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+ clk_disable(&priv->ref_clk_n);
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+ clk_disable(&priv->pclk);
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+ reset_assert(&priv->p30phy);
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+
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+ return 0;
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+}
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+
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+static int rockchip_p3phy_probe(struct udevice *dev)
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+{
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+ struct rockchip_p3phy_priv *priv = dev_get_priv(dev);
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+ struct udevice *syscon;
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+ int ret;
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+
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+ priv->mmio = (void __iomem *)dev_read_addr(dev);
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+ if ((fdt_addr_t)priv->mmio == FDT_ADDR_T_NONE)
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+ return -EINVAL;
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+
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+ ret = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
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+ "rockchip,phy-grf", &syscon);
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+ if (ret) {
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+ pr_err("unable to find syscon device for rockchip,phy-grf\n");
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+ return ret;
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+ }
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+
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+ priv->phy_grf = syscon_get_regmap(syscon);
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+ if (IS_ERR(priv->phy_grf)) {
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+ dev_err(dev, "failed to find rockchip,phy_grf regmap\n");
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+ return PTR_ERR(priv->phy_grf);
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+ }
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+
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+ ret = reset_get_by_name(dev, "phy", &priv->p30phy);
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+ if (ret) {
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+ dev_err(dev, "no phy reset control specified\n");
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+ return ret;
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+ }
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+
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+ ret = clk_get_by_name(dev, "refclk_m", &priv->ref_clk_m);
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+ if (ret) {
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+ dev_err(dev, "failed to find ref clock M\n");
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+ return PTR_ERR(&priv->ref_clk_m);
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+ }
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+
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+ ret = clk_get_by_name(dev, "refclk_n", &priv->ref_clk_n);
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+ if (ret) {
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+ dev_err(dev, "failed to find ref clock N\n");
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+ return PTR_ERR(&priv->ref_clk_n);
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+ }
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+
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+ ret = clk_get_by_name(dev, "pclk", &priv->pclk);
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+ if (ret) {
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+ dev_err(dev, "failed to find pclk\n");
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+ return PTR_ERR(&priv->pclk);
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+ }
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+
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+ return 0;
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+}
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+
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+static struct phy_ops rochchip_p3phy_ops = {
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+ .init = rochchip_p3phy_init,
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+ .exit = rochchip_p3phy_exit,
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+};
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+
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+static const struct udevice_id rockchip_p3phy_of_match[] = {
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+ { .compatible = "rockchip,rk3568-pcie3-phy" },
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+ { },
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+};
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+
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+U_BOOT_DRIVER(rockchip_pcie3phy) = {
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+ .name = "rockchip_pcie3phy",
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+ .id = UCLASS_PHY,
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+ .of_match = rockchip_p3phy_of_match,
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+ .ops = &rochchip_p3phy_ops,
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+ .probe = rockchip_p3phy_probe,
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+ .priv_auto = sizeof(struct rockchip_p3phy_priv),
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+};
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