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@@ -0,0 +1,224 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
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+ */
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+#include <asm/arch-rockchip/hardware.h>
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+#include <asm/io.h>
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+#include <common.h>
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+#include <dm.h>
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+#include <linux/iopoll.h>
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+#include <linux/string.h>
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+#include <rng.h>
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+
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+#define RK_HW_RNG_MAX 32
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+
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+#define _SBF(s, v) ((v) << (s))
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+
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+/* start of CRYPTO V1 register define */
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+#define CRYPTO_V1_CTRL 0x0008
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+#define CRYPTO_V1_RNG_START BIT(8)
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+#define CRYPTO_V1_RNG_FLUSH BIT(9)
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+
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+#define CRYPTO_V1_TRNG_CTRL 0x0200
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+#define CRYPTO_V1_OSC_ENABLE BIT(16)
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+#define CRYPTO_V1_TRNG_SAMPLE_PERIOD(x) (x)
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+
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+#define CRYPTO_V1_TRNG_DOUT_0 0x0204
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+/* end of CRYPTO V1 register define */
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+
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+/* start of CRYPTO V2 register define */
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+#define CRYPTO_V2_RNG_CTL 0x0400
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+#define CRYPTO_V2_RNG_64_BIT_LEN _SBF(4, 0x00)
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+#define CRYPTO_V2_RNG_128_BIT_LEN _SBF(4, 0x01)
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+#define CRYPTO_V2_RNG_192_BIT_LEN _SBF(4, 0x02)
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+#define CRYPTO_V2_RNG_256_BIT_LEN _SBF(4, 0x03)
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+#define CRYPTO_V2_RNG_FATESY_SOC_RING _SBF(2, 0x00)
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+#define CRYPTO_V2_RNG_SLOWER_SOC_RING_0 _SBF(2, 0x01)
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+#define CRYPTO_V2_RNG_SLOWER_SOC_RING_1 _SBF(2, 0x02)
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+#define CRYPTO_V2_RNG_SLOWEST_SOC_RING _SBF(2, 0x03)
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+#define CRYPTO_V2_RNG_ENABLE BIT(1)
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+#define CRYPTO_V2_RNG_START BIT(0)
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+#define CRYPTO_V2_RNG_SAMPLE_CNT 0x0404
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+#define CRYPTO_V2_RNG_DOUT_0 0x0410
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+/* end of CRYPTO V2 register define */
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+
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+#define RK_RNG_TIME_OUT 50000 /* max 50ms */
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+
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+struct rk_rng_soc_data {
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+ int (*rk_rng_read)(struct udevice *dev, void *data, size_t len);
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+};
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+
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+struct rk_rng_platdata {
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+ fdt_addr_t base;
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+ struct rk_rng_soc_data *soc_data;
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+};
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+
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+static int rk_rng_read_regs(fdt_addr_t addr, void *buf, size_t size)
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+{
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+ u32 count = RK_HW_RNG_MAX / sizeof(u32);
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+ u32 reg, tmp_len;
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+
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+ if (size > RK_HW_RNG_MAX)
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+ return -EINVAL;
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+
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+ while (size && count) {
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+ reg = readl(addr);
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+ tmp_len = min(size, sizeof(u32));
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+ memcpy(buf, ®, tmp_len);
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+ addr += sizeof(u32);
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+ buf += tmp_len;
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+ size -= tmp_len;
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+ count--;
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+ }
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+
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+ return 0;
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+}
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+
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+static int rk_v1_rng_read(struct udevice *dev, void *data, size_t len)
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+{
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+ struct rk_rng_platdata *pdata = dev_get_priv(dev);
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+ u32 reg = 0;
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+ int retval;
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+
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+ if (len > RK_HW_RNG_MAX)
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+ return -EINVAL;
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+
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+ /* enable osc_ring to get entropy, sample period is set as 100 */
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+ writel(CRYPTO_V1_OSC_ENABLE | CRYPTO_V1_TRNG_SAMPLE_PERIOD(100),
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+ pdata->base + CRYPTO_V1_TRNG_CTRL);
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+
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+ rk_clrsetreg(pdata->base + CRYPTO_V1_CTRL, CRYPTO_V1_RNG_START,
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+ CRYPTO_V1_RNG_START);
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+
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+ retval = readl_poll_timeout(pdata->base + CRYPTO_V1_CTRL, reg,
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+ !(reg & CRYPTO_V1_RNG_START),
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+ RK_RNG_TIME_OUT);
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+ if (retval)
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+ goto exit;
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+
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+ rk_rng_read_regs(pdata->base + CRYPTO_V1_TRNG_DOUT_0, data, len);
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+
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+exit:
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+ /* close TRNG */
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+ rk_clrreg(pdata->base + CRYPTO_V1_CTRL, CRYPTO_V1_RNG_START);
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+
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+ return 0;
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+}
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+
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+static int rk_v2_rng_read(struct udevice *dev, void *data, size_t len)
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+{
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+ struct rk_rng_platdata *pdata = dev_get_priv(dev);
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+ u32 reg = 0;
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+ int retval;
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+
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+ if (len > RK_HW_RNG_MAX)
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+ return -EINVAL;
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+
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+ /* enable osc_ring to get entropy, sample period is set as 100 */
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+ writel(100, pdata->base + CRYPTO_V2_RNG_SAMPLE_CNT);
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+
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+ reg |= CRYPTO_V2_RNG_256_BIT_LEN;
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+ reg |= CRYPTO_V2_RNG_SLOWER_SOC_RING_0;
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+ reg |= CRYPTO_V2_RNG_ENABLE;
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+ reg |= CRYPTO_V2_RNG_START;
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+
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+ rk_clrsetreg(pdata->base + CRYPTO_V2_RNG_CTL, 0xffff, reg);
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+
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+ retval = readl_poll_timeout(pdata->base + CRYPTO_V2_RNG_CTL, reg,
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+ !(reg & CRYPTO_V2_RNG_START),
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+ RK_RNG_TIME_OUT);
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+ if (retval)
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+ goto exit;
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+
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+ rk_rng_read_regs(pdata->base + CRYPTO_V2_RNG_DOUT_0, data, len);
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+
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+exit:
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+ /* close TRNG */
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+ rk_clrreg(pdata->base + CRYPTO_V2_RNG_CTL, 0xffff);
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+
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+ return retval;
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+}
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+
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+static int rockchip_rng_read(struct udevice *dev, void *data, size_t len)
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+{
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+ unsigned char *buf = data;
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+ unsigned int i;
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+ int ret = -EIO;
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+
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+ struct rk_rng_platdata *pdata = dev_get_priv(dev);
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+
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+ if (!len)
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+ return 0;
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+
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+ if (!pdata->soc_data || !pdata->soc_data->rk_rng_read)
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+ return -EINVAL;
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+
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+ for (i = 0; i < len / RK_HW_RNG_MAX; i++, buf += RK_HW_RNG_MAX) {
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+ ret = pdata->soc_data->rk_rng_read(dev, buf, RK_HW_RNG_MAX);
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+ if (ret)
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+ goto exit;
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+ }
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+
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+ if (len % RK_HW_RNG_MAX)
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+ ret = pdata->soc_data->rk_rng_read(dev, buf,
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+ len % RK_HW_RNG_MAX);
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+
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+exit:
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+ return ret;
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+}
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+
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+static int rockchip_rng_ofdata_to_platdata(struct udevice *dev)
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+{
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+ struct rk_rng_platdata *pdata = dev_get_priv(dev);
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+
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+ memset(pdata, 0x00, sizeof(*pdata));
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+
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+ pdata->base = (fdt_addr_t)dev_read_addr_ptr(dev);
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+ if (!pdata->base)
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+ return -ENOMEM;
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+
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+ return 0;
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+}
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+
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+static int rockchip_rng_probe(struct udevice *dev)
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+{
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+ struct rk_rng_platdata *pdata = dev_get_priv(dev);
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+
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+ pdata->soc_data = (struct rk_rng_soc_data *)dev_get_driver_data(dev);
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+
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+ return 0;
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+}
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+
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+static const struct rk_rng_soc_data rk_rng_v1_soc_data = {
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+ .rk_rng_read = rk_v1_rng_read,
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+};
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+
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+static const struct rk_rng_soc_data rk_rng_v2_soc_data = {
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+ .rk_rng_read = rk_v2_rng_read,
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+};
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+
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+static const struct dm_rng_ops rockchip_rng_ops = {
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+ .read = rockchip_rng_read,
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+};
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+
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+static const struct udevice_id rockchip_rng_match[] = {
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+ {
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+ .compatible = "rockchip,cryptov1-rng",
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+ .data = (ulong)&rk_rng_v1_soc_data,
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+ },
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+ {
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+ .compatible = "rockchip,cryptov2-rng",
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+ .data = (ulong)&rk_rng_v2_soc_data,
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+ },
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+ {},
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+};
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+
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+U_BOOT_DRIVER(rockchip_rng) = {
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+ .name = "rockchip-rng",
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+ .id = UCLASS_RNG,
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+ .of_match = rockchip_rng_match,
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+ .ops = &rockchip_rng_ops,
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+ .probe = rockchip_rng_probe,
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+ .ofdata_to_platdata = rockchip_rng_ofdata_to_platdata,
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+ .priv_auto_alloc_size = sizeof(struct rk_rng_platdata),
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+};
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