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@@ -7,6 +7,7 @@
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#include <console.h>
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#include <dfu.h>
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#include <malloc.h>
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+#include <misc.h>
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#include <mmc.h>
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#include <part.h>
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#include <asm/arch/stm32mp1_smc.h>
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@@ -1107,7 +1108,7 @@ static int dfu_init_entities(struct stm32prog_data *data)
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struct dfu_entity *dfu;
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int alt_nb;
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- alt_nb = 2; /* number of virtual = CMD, OTP*/
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+ alt_nb = 3; /* number of virtual = CMD, OTP, PMIC*/
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if (data->part_nb == 0)
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alt_nb++; /* +1 for FlashLayout */
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else
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@@ -1158,6 +1159,9 @@ static int dfu_init_entities(struct stm32prog_data *data)
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if (!ret)
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ret = stm32prog_alt_add_virt(dfu, "OTP", PHASE_OTP, 512);
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+ if (!ret && CONFIG_IS_ENABLED(DM_PMIC))
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+ ret = stm32prog_alt_add_virt(dfu, "PMIC", PHASE_PMIC, 8);
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+
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if (ret)
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stm32prog_err("dfu init failed: %d", ret);
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puts("done\n");
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@@ -1285,6 +1289,93 @@ int stm32prog_otp_start(struct stm32prog_data *data)
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#endif
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}
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+int stm32prog_pmic_write(struct stm32prog_data *data, u32 offset, u8 *buffer,
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+ long *size)
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+{
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+ pr_debug("%s: %x %lx\n", __func__, offset, *size);
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+
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+ if (!offset)
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+ memset(data->pmic_part, 0, PMIC_SIZE);
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+
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+ if (offset + *size > PMIC_SIZE)
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+ *size = PMIC_SIZE - offset;
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+
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+ memcpy(&data->pmic_part[offset], buffer, *size);
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+
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+ return 0;
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+}
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+
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+int stm32prog_pmic_read(struct stm32prog_data *data, u32 offset, u8 *buffer,
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+ long *size)
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+{
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+ int result = 0, ret;
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+ struct udevice *dev;
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+
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+ if (!CONFIG_IS_ENABLED(PMIC_STPMIC1)) {
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+ stm32prog_err("PMIC update not supported");
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+
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+ return -EOPNOTSUPP;
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+ }
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+
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+ pr_debug("%s: %x %lx\n", __func__, offset, *size);
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+ ret = uclass_get_device_by_driver(UCLASS_MISC,
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+ DM_GET_DRIVER(stpmic1_nvm),
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+ &dev);
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+ if (ret)
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+ return ret;
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+
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+ /* alway request PMIC for first packet */
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+ if (!offset) {
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+ /* init struct with 0 */
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+ memset(data->pmic_part, 0, PMIC_SIZE);
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+
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+ ret = uclass_get_device_by_driver(UCLASS_MISC,
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+ DM_GET_DRIVER(stpmic1_nvm),
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+ &dev);
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+ if (ret)
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+ return ret;
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+
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+ ret = misc_read(dev, 0xF8, data->pmic_part, PMIC_SIZE);
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+ if (ret < 0) {
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+ result = ret;
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+ goto end_pmic_read;
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+ }
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+ if (ret != PMIC_SIZE) {
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+ result = -EACCES;
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+ goto end_pmic_read;
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+ }
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+ }
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+
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+ if (offset + *size > PMIC_SIZE)
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+ *size = PMIC_SIZE - offset;
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+
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+ memcpy(buffer, &data->pmic_part[offset], *size);
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+
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+end_pmic_read:
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+ pr_debug("%s: result %i\n", __func__, result);
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+ return result;
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+}
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+
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+int stm32prog_pmic_start(struct stm32prog_data *data)
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+{
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+ int ret;
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+ struct udevice *dev;
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+
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+ if (!CONFIG_IS_ENABLED(PMIC_STPMIC1)) {
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+ stm32prog_err("PMIC update not supported");
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+
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+ return -EOPNOTSUPP;
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+ }
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+
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+ ret = uclass_get_device_by_driver(UCLASS_MISC,
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+ DM_GET_DRIVER(stpmic1_nvm),
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+ &dev);
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+ if (ret)
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+ return ret;
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+
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+ return misc_write(dev, 0xF8, data->pmic_part, PMIC_SIZE);
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+}
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+
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/* copy FSBL on NAND to improve reliability on NAND */
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static int stm32prog_copy_fsbl(struct stm32prog_part_t *part)
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{
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@@ -1585,6 +1676,8 @@ void dfu_flush_callback(struct dfu_entity *dfu)
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if (dfu->dev_type == DFU_DEV_VIRT) {
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if (dfu->data.virt.dev_num == PHASE_OTP)
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stm32prog_otp_start(stm32prog_data);
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+ else if (dfu->data.virt.dev_num == PHASE_PMIC)
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+ stm32prog_pmic_start(stm32prog_data);
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return;
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}
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