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@@ -151,6 +151,19 @@ int fdtdec_board_setup(const void *fdt_blob)
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return fixup_usb_boot();
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}
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#endif
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+
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+static void setup_am654_navss_northbridge(void)
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+{
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+ /*
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+ * NB0 is bridge to SRAM and NB1 is bridge to DDR.
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+ * To ensure that SRAM transfers are not stalled due to
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+ * delays during DDR refreshes, SRAM traffic should be higher
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+ * priority (threadmap=2) than DDR traffic (threadmap=0).
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+ */
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+ writel(0x2, NAVSS0_NBSS_NB0_CFG_BASE + NAVSS_NBSS_THREADMAP);
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+ writel(0x0, NAVSS0_NBSS_NB1_CFG_BASE + NAVSS_NBSS_THREADMAP);
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+}
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+
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void board_init_f(ulong dummy)
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{
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#if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM654_DDRSS)
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@@ -168,6 +181,8 @@ void board_init_f(ulong dummy)
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/* Make all control module registers accessible */
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ctrl_mmr_unlock();
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+ setup_am654_navss_northbridge();
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+
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#ifdef CONFIG_CPU_V7R
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disable_linefill_optimization();
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setup_k3_mpu_regions();
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