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@@ -363,7 +363,7 @@ static u32 versal_clock_get_div(u32 clk_id)
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u32 ret_payload[PAYLOAD_ARG_CNT];
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u32 div;
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- versal_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
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+ xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
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div = ret_payload[1];
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return div;
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@@ -373,7 +373,7 @@ static u32 versal_clock_set_div(u32 clk_id, u32 div)
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{
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u32 ret_payload[PAYLOAD_ARG_CNT];
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- versal_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, ret_payload);
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+ xilinx_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, ret_payload);
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return div;
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}
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@@ -383,7 +383,7 @@ static u64 versal_clock_ref(u32 clk_id)
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u32 ret_payload[PAYLOAD_ARG_CNT];
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int ref;
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- versal_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload);
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+ xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload);
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ref = ret_payload[0];
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if (!(ref & 1))
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return ref_clk;
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@@ -402,7 +402,7 @@ static u64 versal_clock_get_pll_rate(u32 clk_id)
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u32 parent_rate, parent_id;
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u32 id = clk_id & 0xFFF;
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- versal_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload);
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+ xilinx_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload);
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res = ret_payload[1];
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if (!res) {
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printf("0%x PLL not enabled\n", clk_id);
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@@ -412,9 +412,9 @@ static u64 versal_clock_get_pll_rate(u32 clk_id)
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parent_id = clock[clock[id].parent[0].id].clk_id;
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parent_rate = versal_clock_ref(parent_id);
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- versal_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
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+ xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
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fbdiv = ret_payload[1];
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- versal_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload);
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+ xilinx_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload);
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frac = ret_payload[1];
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freq = (fbdiv * parent_rate) >> (1 << frac);
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@@ -441,7 +441,7 @@ static u32 versal_clock_get_parentid(u32 clk_id)
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u32 id = clk_id & 0xFFF;
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if (versal_clock_mux(clk_id)) {
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- versal_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0,
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+ xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0,
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ret_payload);
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parent_id = ret_payload[1];
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}
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