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@@ -251,6 +251,8 @@ static u8 spi_nor_convert_3to4_read(u8 opcode)
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{ SPINOR_OP_READ_1_2_2, SPINOR_OP_READ_1_2_2_4B },
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{ SPINOR_OP_READ_1_1_4, SPINOR_OP_READ_1_1_4_4B },
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{ SPINOR_OP_READ_1_4_4, SPINOR_OP_READ_1_4_4_4B },
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+ { SPINOR_OP_READ_1_1_8, SPINOR_OP_READ_1_1_8_4B },
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+ { SPINOR_OP_READ_1_8_8, SPINOR_OP_READ_1_8_8_4B },
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{ SPINOR_OP_READ_1_1_1_DTR, SPINOR_OP_READ_1_1_1_DTR_4B },
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{ SPINOR_OP_READ_1_2_2_DTR, SPINOR_OP_READ_1_2_2_DTR_4B },
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@@ -267,6 +269,8 @@ static u8 spi_nor_convert_3to4_program(u8 opcode)
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{ SPINOR_OP_PP, SPINOR_OP_PP_4B },
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{ SPINOR_OP_PP_1_1_4, SPINOR_OP_PP_1_1_4_4B },
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{ SPINOR_OP_PP_1_4_4, SPINOR_OP_PP_1_4_4_4B },
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+ { SPINOR_OP_PP_1_1_8, SPINOR_OP_PP_1_1_8_4B },
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+ { SPINOR_OP_PP_1_8_8, SPINOR_OP_PP_1_8_8_4B },
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};
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return spi_nor_convert_opcode(opcode, spi_nor_3to4_program,
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@@ -2169,6 +2173,13 @@ static int spi_nor_init_params(struct spi_nor *nor,
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SNOR_PROTO_1_1_4);
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}
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+ if (info->flags & SPI_NOR_OCTAL_READ) {
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+ params->hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
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+ spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_8],
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+ 0, 8, SPINOR_OP_READ_1_1_8,
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+ SNOR_PROTO_1_1_8);
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+ }
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+
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/* Page Program settings. */
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params->hwcaps.mask |= SNOR_HWCAPS_PP;
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spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
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@@ -2476,7 +2487,14 @@ int spi_nor_scan(struct spi_nor *nor)
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nor->read_reg = spi_nor_read_reg;
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nor->write_reg = spi_nor_write_reg;
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- if (spi->mode & SPI_RX_QUAD) {
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+ if (spi->mode & SPI_RX_OCTAL) {
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+ hwcaps.mask |= SNOR_HWCAPS_READ_1_1_8;
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+
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+ if (spi->mode & SPI_TX_OCTAL)
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+ hwcaps.mask |= (SNOR_HWCAPS_READ_1_8_8 |
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+ SNOR_HWCAPS_PP_1_1_8 |
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+ SNOR_HWCAPS_PP_1_8_8);
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+ } else if (spi->mode & SPI_RX_QUAD) {
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hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
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if (spi->mode & SPI_TX_QUAD)
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