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board: starfive: Add i2c5 init for VisionFive2

Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Jianlong Huang 1 year ago
parent
commit
6425663515

+ 13 - 0
arch/riscv/dts/jh7110.dtsi

@@ -614,6 +614,19 @@
 			status = "disabled";
 		};
 
+		i2c5: i2c@12050000 {
+			compatible = "snps,designware-i2c";
+			reg = <0x0 0x12050000 0x0 0x10000>;
+			clocks = <&clkgen JH7110_I2C5_CLK_CORE>,
+				 <&clkgen JH7110_I2C5_CLK_APB>;
+			clock-names = "ref", "pclk";
+			resets = <&rstgen RSTN_U5_DW_I2C_APB>;
+			interrupts = <50>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		/* unremovable emmc as mmcblk0 */
 		sdio0: sdio0@16010000 {
 			compatible = "snps,dw-mshc";

+ 16 - 0
arch/riscv/dts/starfive_visionfive2.dts

@@ -19,6 +19,7 @@
 		ethernet1=&gmac1;
 		mmc0=&sdio0;
 		mmc1=&sdio1;
+		i2c5 = &i2c5;
 	};
 
 	chosen {
@@ -91,6 +92,21 @@
 	status = "okay";
 };
 
+&i2c5 {
+	clock-frequency = <100000>;
+	i2c-sda-hold-time-ns = <300>;
+	i2c-sda-falling-time-ns = <3000>;
+	i2c-scl-falling-time-ns = <3000>;
+	auto_calc_scl_lhcnt;
+	status = "okay";
+
+	eeprom@50 {
+		compatible = "atmel,24c04";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
+};
+
 &gpioa {
 	status = "disabled";
 };

+ 17 - 0
board/starfive/visionfive2/starfive_visionfive2.c

@@ -193,6 +193,22 @@ static void jh7110_jtag_init(void)
 	SYS_IOMUX_DOUT(44, 22);
 }
 
+static void jh7110_i2c_init(int id)
+{
+	switch (id) {
+	case 5:
+		//scl
+		SYS_IOMUX_COMPLEX(19, 79, 0, 42);
+		//sda
+		SYS_IOMUX_COMPLEX(20, 80, 0, 43);
+
+		break;
+
+	default:
+		break;
+	}
+}
+
 int board_init(void)
 {
 	enable_caches();
@@ -210,6 +226,7 @@ int board_init(void)
 
 	jh7110_mmc_init(0);
 	jh7110_mmc_init(1);
+	jh7110_i2c_init(5);
 
 	return 0;
 }

+ 10 - 0
drivers/clk/starfive/clk-jh7110.c

@@ -604,6 +604,16 @@ static int jh7110_clk_init(struct udevice *dev)
 			"u0_otpc_clk_apb",	"aon_apb",
 			AON_OFFSET(JH7110_OTPC_CLK_APB)));
 
+	/*i2c5*/
+	clk_dm(JH7110_I2C5_CLK_APB,
+		starfive_clk_gate(priv->sys,
+			"u5_dw_i2c_clk_apb", "apb0",
+			SYS_OFFSET(JH7110_I2C5_CLK_APB)));
+	clk_dm(JH7110_I2C5_CLK_CORE,
+		starfive_clk_gate(priv->sys,
+			"u5_dw_i2c_clk_core", "osc",
+			SYS_OFFSET(JH7110_I2C5_CLK_CORE)));
+
 	return 0;
 }
 

+ 9 - 5
drivers/i2c/designware_i2c.c

@@ -775,10 +775,14 @@ int designware_i2c_of_to_plat(struct udevice *bus)
 	if (ret)
 		return ret;
 
-	ret = clk_enable(&priv->clk);
+	ret = clk_get_bulk(bus, &priv->clks);
+	if (ret)
+		return ret;
+
+	ret = clk_enable_bulk(&priv->clks);
 	if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
-		clk_free(&priv->clk);
-		dev_err(bus, "failed to enable clock\n");
+		clk_release_bulk(&priv->clks);
+		dev_err(bus, "failed to enable bulk clock\n");
 		return ret;
 	}
 #endif
@@ -809,8 +813,8 @@ int designware_i2c_remove(struct udevice *dev)
 	struct dw_i2c *priv = dev_get_priv(dev);
 
 #if CONFIG_IS_ENABLED(CLK)
-	clk_disable(&priv->clk);
-	clk_free(&priv->clk);
+	clk_disable_bulk(&priv->clks);
+	clk_release_bulk(&priv->clks);
 #endif
 
 	return reset_release_bulk(&priv->resets);

+ 1 - 0
drivers/i2c/designware_i2c.h

@@ -204,6 +204,7 @@ struct dw_i2c {
 	bool has_spk_cnt;
 #if CONFIG_IS_ENABLED(CLK)
 	struct clk clk;
+	struct clk_bulk clks;
 #endif
 	struct dw_i2c_speed_config config;
 };