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@@ -21,6 +21,7 @@ DECLARE_GLOBAL_DATA_PTR;
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#define SITES_MAX 16
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#define FLAGS_VER2 0x1
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+#define FLAGS_VER3 0x2
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#define TMR_DISABLE 0x0
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#define TMR_ME 0x80000000
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@@ -30,6 +31,8 @@ DECLARE_GLOBAL_DATA_PTR;
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#define TER_EN 0x80000000
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#define TER_ADC_PD 0x40000000
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+#define TER_ALPF 0x3
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+
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/*
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* i.MX TMU Registers
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*/
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@@ -86,9 +89,29 @@ struct imx_tmu_regs_v2 {
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u32 tcaliv;
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};
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+struct imx_tmu_regs_v3 {
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+ u32 ter; /* TMU enable Register */
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+ u32 tps; /* Status Register */
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+ u32 tier; /* Interrupt enable register */
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+ u32 tidr; /* Interrupt detect register */
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+ u32 tmhtitr; /* Monitor high temperature immediate threshold register */
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+ u32 tmhtatr; /* Monitor high temperature average threshold register */
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+ u32 tmhtactr; /* TMU monitor high temperature average critical threshold register */
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+ u32 tscr; /* Sensor value capture register */
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+ u32 tritsr; /* Report immediate temperature site register 0 */
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+ u32 tratsr; /* Report average temperature site register 0 */
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+ u32 tasr; /* Amplifier setting register */
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+ u32 ttmc; /* Test MUX control */
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+ u32 tcaliv0;
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+ u32 tcaliv1;
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+ u32 tcaliv_m40;
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+ u32 trim;
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+};
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+
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union tmu_regs {
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struct imx_tmu_regs regs_v1;
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struct imx_tmu_regs_v2 regs_v2;
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+ struct imx_tmu_regs_v3 regs_v3;
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};
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struct imx_tmu_plat {
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@@ -112,7 +135,10 @@ static int read_temperature(struct udevice *dev, int *temp)
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mdelay(100);
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retry--;
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- if (drv_data & FLAGS_VER2) {
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+ if (drv_data & FLAGS_VER3) {
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+ val = readl(&pdata->regs->regs_v3.tritsr);
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+ valid = val & (1 << (30 + pdata->id));
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+ } else if (drv_data & FLAGS_VER2) {
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val = readl(&pdata->regs->regs_v2.tritsr);
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/*
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* Check if TEMP is in valid range, the V bit in TRITSR
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@@ -125,10 +151,23 @@ static int read_temperature(struct udevice *dev, int *temp)
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}
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} while (!valid && retry > 0);
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- if (retry > 0)
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- *temp = (val & 0xff) * 1000;
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- else
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+ if (retry > 0) {
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+ if (drv_data & FLAGS_VER3) {
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+ val = (val >> (pdata->id * 16)) & 0xff;
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+ if (val & 0x80) /* Negative */
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+ val = (~(val & 0x7f) + 1);
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+
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+ *temp = val;
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+ if (*temp < -40 || *temp > 125) /* Check the range */
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+ return -EINVAL;
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+
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+ *temp *= 1000;
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+ } else {
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+ *temp = (val & 0xff) * 1000;
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+ }
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+ } else {
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return -EINVAL;
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+ }
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return 0;
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}
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@@ -171,7 +210,7 @@ static int imx_tmu_calibration(struct udevice *dev)
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debug("%s\n", __func__);
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- if (drv_data & FLAGS_VER2)
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+ if (drv_data & (FLAGS_VER2 | FLAGS_VER3))
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return 0;
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ret = dev_read_u32_array(dev, "fsl,tmu-range", range, 4);
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@@ -213,7 +252,14 @@ static void imx_tmu_init(struct udevice *dev)
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debug("%s\n", __func__);
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- if (drv_data & FLAGS_VER2) {
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+ if (drv_data & FLAGS_VER3) {
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+ /* Disable monitoring */
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+ writel(0x0, &pdata->regs->regs_v3.ter);
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+
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+ /* Disable interrupt, using polling instead */
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+ writel(0x0, &pdata->regs->regs_v3.tier);
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+
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+ } else if (drv_data & FLAGS_VER2) {
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/* Disable monitoring */
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writel(0x0, &pdata->regs->regs_v2.ter);
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@@ -244,7 +290,22 @@ static int imx_tmu_enable_msite(struct udevice *dev)
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if (!pdata->regs)
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return -EIO;
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- if (drv_data & FLAGS_VER2) {
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+ if (drv_data & FLAGS_VER3) {
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+ reg = readl(&pdata->regs->regs_v3.ter);
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+ reg &= ~TER_EN;
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+ writel(reg, &pdata->regs->regs_v3.ter);
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+
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+ writel(pdata->id << 30, &pdata->regs->regs_v3.tps);
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+
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+ reg &= ~TER_ALPF;
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+ reg |= 0x1;
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+ reg &= ~TER_ADC_PD;
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+ writel(reg, &pdata->regs->regs_v3.ter);
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+
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+ /* Enable monitor */
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+ reg |= TER_EN;
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+ writel(reg, &pdata->regs->regs_v3.ter);
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+ } else if (drv_data & FLAGS_VER2) {
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reg = readl(&pdata->regs->regs_v2.ter);
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reg &= ~TER_EN;
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writel(reg, &pdata->regs->regs_v2.ter);
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@@ -390,6 +451,7 @@ static int imx_tmu_probe(struct udevice *dev)
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static const struct udevice_id imx_tmu_ids[] = {
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{ .compatible = "fsl,imx8mq-tmu", },
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{ .compatible = "fsl,imx8mm-tmu", .data = FLAGS_VER2, },
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+ { .compatible = "fsl,imx8mp-tmu", .data = FLAGS_VER3, },
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{ }
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};
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