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@@ -20,24 +20,28 @@
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DECLARE_GLOBAL_DATA_PTR;
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-int cache_enable_ways(void)
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+static fdt_addr_t l2cc_get_base_addr(void)
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{
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const void *blob = gd->fdt_blob;
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- int node;
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+ int node = fdt_node_offset_by_compatible(blob, -1,
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+ "sifive,fu540-c000-ccache");
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+
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+ if (node < 0)
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+ return FDT_ADDR_T_NONE;
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+
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+ return fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
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+ NULL, false);
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+}
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+
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+int cache_enable_ways(void)
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+{
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fdt_addr_t base;
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u32 config;
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u32 ways;
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volatile u32 *enable;
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- node = fdt_node_offset_by_compatible(blob, -1,
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- "sifive,fu540-c000-ccache");
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-
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- if (node < 0)
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- return node;
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-
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- base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
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- NULL, false);
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+ base = l2cc_get_base_addr();
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if (base == FDT_ADDR_T_NONE)
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return FDT_ADDR_T_NONE;
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@@ -53,3 +57,36 @@ int cache_enable_ways(void)
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mb();
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return 0;
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}
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+
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+#if CONFIG_IS_ENABLED(SIFIVE_FU540_L2CC_FLUSH)
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+#define L2_CACHE_FLUSH64 0x200
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+
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+void flush_dcache_range(unsigned long start, unsigned long end)
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+{
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+ fdt_addr_t base;
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+ unsigned long line;
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+ volatile unsigned long *flush64;
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+
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+ /* make sure the address is in the range */
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+ if(start > end ||
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+ start < CONFIG_SIFIVE_FU540_L2CC_FLUSH_START ||
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+ end > (CONFIG_SIFIVE_FU540_L2CC_FLUSH_START +
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+ CONFIG_SIFIVE_FU540_L2CC_FLUSH_SIZE))
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+ return;
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+
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+ base = l2cc_get_base_addr();
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+ if (base == FDT_ADDR_T_NONE)
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+ return;
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+
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+ flush64 = (volatile unsigned long *)(base + L2_CACHE_FLUSH64);
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+
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+ /* memory barrier */
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+ mb();
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+ for (line = start; line < end; line += CONFIG_SYS_CACHELINE_SIZE)
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+ (*flush64) = line;
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+ /* memory barrier */
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+ mb();
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+
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+ return;
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+}
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+#endif //SIFIVE_FU540_L2CC_FLUSH
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