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board:starfive:evb: update uart3-uart5 resets

Add SPL_DM_RESET to defconfig, and update uart3-uart5 reset for StarFive
JH7110 SoC.

Signed-off-by: yanhong.wang <yanhong.wang@starfivetech.com>
yanhong.wang 2 years ago
parent
commit
61f294b11c
2 changed files with 13 additions and 6 deletions
  1. 12 6
      arch/riscv/dts/jh7110.dtsi
  2. 1 0
      configs/starfive_evb_defconfig

+ 12 - 6
arch/riscv/dts/jh7110.dtsi

@@ -407,7 +407,8 @@
 			clocks = <&clkgen JH7110_UART0_CLK_CORE>,
 				 <&clkgen JH7110_UART0_CLK_APB>;
 			clock-names = "baudclk", "apb_pclk";
-			resets = <&rstgen RSTN_U0_DW_UART_APB>;
+			resets = <&rstgen RSTN_U0_DW_UART_APB>,
+				<&rstgen RSTN_U0_DW_UART_CORE>;
 			interrupts = <32>;
 			status = "disabled";
 		};
@@ -420,7 +421,8 @@
 			clocks = <&clkgen JH7110_UART1_CLK_CORE>,
 				 <&clkgen JH7110_UART1_CLK_APB>;
 			clock-names = "baudclk", "apb_pclk";
-			resets = <&rstgen RSTN_U1_DW_UART_APB>;
+			resets = <&rstgen RSTN_U1_DW_UART_APB>,
+				<&rstgen RSTN_U1_DW_UART_CORE>;
 			interrupts = <33>;
 			status = "disabled";
 		};
@@ -433,7 +435,8 @@
 			clocks = <&clkgen JH7110_UART2_CLK_CORE>,
 				 <&clkgen JH7110_UART2_CLK_APB>;
 			clock-names = "baudclk", "apb_pclk";
-			resets = <&rstgen RSTN_U2_DW_UART_APB>;
+			resets = <&rstgen RSTN_U2_DW_UART_APB>,
+				<&rstgen RSTN_U2_DW_UART_CORE>;
 			interrupts = <34>;
 			status = "disabled";
 		};
@@ -446,7 +449,8 @@
 			clocks = <&clkgen JH7110_UART3_CLK_CORE>,
 				 <&clkgen JH7110_UART3_CLK_APB>;
 			clock-names = "baudclk", "apb_pclk";
-			resets = <&rstgen RSTN_U3_DW_UART_APB>;
+			resets = <&rstgen RSTN_U3_DW_UART_APB>,
+				<&rstgen RSTN_U3_DW_UART_CORE>;
 			interrupts = <45>;
 			status = "disabled";
 		};
@@ -459,7 +463,8 @@
 			clocks = <&clkgen JH7110_UART4_CLK_CORE>,
 				 <&clkgen JH7110_UART4_CLK_APB>;
 			clock-names = "baudclk", "apb_pclk";
-			resets = <&rstgen RSTN_U4_DW_UART_APB>;
+			resets = <&rstgen RSTN_U4_DW_UART_APB>,
+				<&rstgen RSTN_U4_DW_UART_CORE>;
 			interrupts = <46>;
 			status = "disabled";
 		};
@@ -472,7 +477,8 @@
 			clocks = <&clkgen JH7110_UART5_CLK_CORE>,
 				 <&clkgen JH7110_UART5_CLK_APB>;
 			clock-names = "baudclk", "apb_pclk";
-			resets = <&rstgen RSTN_U5_DW_UART_APB>;
+			resets = <&rstgen RSTN_U5_DW_UART_APB>,
+				<&rstgen RSTN_U5_DW_UART_CORE>;
 			interrupts = <47>;
 			status = "disabled";
 		};

+ 1 - 0
configs/starfive_evb_defconfig

@@ -33,6 +33,7 @@ CONFIG_MISC_INIT_R=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1800
 CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="StarFive # "