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@@ -0,0 +1,368 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * V3MSK board CPLD access support
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+ *
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+ * Copyright (C) 2019 Renesas Electronics Corporation
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+ * Copyright (C) 2019 Cogent Embedded, Inc.
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+ *
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+ */
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+
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+#include <common.h>
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+#include <asm/gpio.h>
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+#include <asm/io.h>
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+#include <dm.h>
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+#include <errno.h>
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+#include <linux/err.h>
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+#include <sysreset.h>
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+#include <linux/delay.h>
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+#include <command.h>
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+
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+#define CPLD_ADDR_PRODUCT_L 0x000 /* R */
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+#define CPLD_ADDR_PRODUCT_H 0x001 /* R */
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+#define CPLD_ADDR_CPLD_VERSION_D 0x002 /* R */
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+#define CPLD_ADDR_CPLD_VERSION_Y 0x003 /* R */
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+#define CPLD_ADDR_MODE_SET_L 0x004 /* R/W */
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+#define CPLD_ADDR_MODE_SET_H 0x005 /* R/W */
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+#define CPLD_ADDR_MODE_APPLIED_L 0x006 /* R */
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+#define CPLD_ADDR_MODE_APPLIED_H 0x007 /* R */
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+#define CPLD_ADDR_DIPSW 0x008 /* R */
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+#define CPLD_ADDR_RESET 0x00A /* R/W */
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+#define CPLD_ADDR_POWER_CFG 0x00B /* R/W */
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+#define CPLD_ADDR_PERI_CFG1 0x00C /* R/W */
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+#define CPLD_ADDR_PERI_CFG2 0x00D /* R/W */
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+#define CPLD_ADDR_LEDS 0x00E /* R/W */
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+#define CPLD_ADDR_PCB_VERSION 0x300 /* R */
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+#define CPLD_ADDR_SOC_VERSION 0x301 /* R */
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+#define CPLD_ADDR_PCB_SN_L 0x302 /* R */
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+#define CPLD_ADDR_PCB_SN_H 0x303 /* R */
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+
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+#define MDIO_DELAY 10 /* microseconds */
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+
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+#define CPLD_MAX_GPIOS 2
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+
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+struct renesas_v3msk_sysreset_priv {
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+ struct gpio_desc miso;
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+ struct gpio_desc mosi;
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+ struct gpio_desc mdc;
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+ struct gpio_desc enablez;
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+ /*
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+ * V3MSK Videobox Mini board has CANFD PHY connected
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+ * we must shutdown this chip to use bb pins
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+ */
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+ struct gpio_desc gpios[CPLD_MAX_GPIOS];
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+};
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+
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+static void mdio_bb_active_mdio(struct renesas_v3msk_sysreset_priv *priv)
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+{
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+ dm_gpio_set_dir_flags(&priv->mosi, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
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+}
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+
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+static void mdio_bb_tristate_mdio(struct renesas_v3msk_sysreset_priv *priv)
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+{
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+ dm_gpio_set_dir_flags(&priv->mosi, GPIOD_IS_IN);
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+}
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+
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+static void mdio_bb_set_mdio(struct renesas_v3msk_sysreset_priv *priv, int val)
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+{
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+ dm_gpio_set_value(&priv->mosi, val);
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+}
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+
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+static int mdio_bb_get_mdio(struct renesas_v3msk_sysreset_priv *priv)
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+{
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+ return dm_gpio_get_value(&priv->miso);
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+}
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+
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+static void mdio_bb_set_mdc(struct renesas_v3msk_sysreset_priv *priv, int val)
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+{
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+ dm_gpio_set_value(&priv->mdc, val);
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+}
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+
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+static void mdio_bb_delay(void)
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+{
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+ udelay(MDIO_DELAY);
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+}
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+
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+/* Send the preamble, address, and register (common to read and write) */
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+static void mdio_bb_pre(struct renesas_v3msk_sysreset_priv *priv,
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+ u8 op, u8 addr, u8 reg)
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+{
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+ int i;
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+
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+ /* 32-bit preamble */
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+ mdio_bb_active_mdio(priv);
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+ mdio_bb_set_mdio(priv, 1);
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+ for (i = 0; i < 32; i++) {
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+ mdio_bb_set_mdc(priv, 0);
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+ mdio_bb_delay();
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+ mdio_bb_set_mdc(priv, 1);
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+ mdio_bb_delay();
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+ }
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+ /* send the ST (2-bits of '01') */
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+ mdio_bb_set_mdio(priv, 0);
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+ mdio_bb_set_mdc(priv, 0);
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+ mdio_bb_delay();
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+ mdio_bb_set_mdc(priv, 1);
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+ mdio_bb_delay();
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+ mdio_bb_set_mdio(priv, 1);
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+ mdio_bb_set_mdc(priv, 0);
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+ mdio_bb_delay();
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+ mdio_bb_set_mdc(priv, 1);
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+ mdio_bb_delay();
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+ /* send the OP (2-bits of Opcode: '10'-read, '01'-write) */
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+ mdio_bb_set_mdio(priv, op >> 1);
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+ mdio_bb_set_mdc(priv, 0);
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+ mdio_bb_delay();
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+ mdio_bb_set_mdc(priv, 1);
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+ mdio_bb_delay();
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+ mdio_bb_set_mdio(priv, op & 1);
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+ mdio_bb_set_mdc(priv, 0);
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+ mdio_bb_delay();
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+ mdio_bb_set_mdc(priv, 1);
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+ mdio_bb_delay();
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+ /* send the PA5 (5-bits of PHY address) */
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+ for (i = 0; i < 5; i++) {
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+ mdio_bb_set_mdio(priv, addr & 0x10); /* MSB first */
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+ mdio_bb_set_mdc(priv, 0);
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+ mdio_bb_delay();
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+ mdio_bb_set_mdc(priv, 1);
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+ mdio_bb_delay();
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+ addr <<= 1;
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+ }
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+ /* send the RA5 (5-bits of register address) */
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+ for (i = 0; i < 5; i++) {
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+ mdio_bb_set_mdio(priv, reg & 0x10); /* MSB first */
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+ mdio_bb_set_mdc(priv, 0);
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+ mdio_bb_delay();
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+ mdio_bb_set_mdc(priv, 1);
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+ mdio_bb_delay();
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+ reg <<= 1;
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+ }
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+}
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+
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+static int mdio_bb_read(struct renesas_v3msk_sysreset_priv *priv,
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+ u8 addr, u8 reg)
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+{
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+ int i;
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+ u16 data = 0;
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+
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+ mdio_bb_pre(priv, 2, addr, reg);
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+ /* tri-state MDIO */
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+ mdio_bb_tristate_mdio(priv);
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+ /* read TA (2-bits of turn-around, last bit must be '0') */
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+ mdio_bb_set_mdc(priv, 0);
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+ mdio_bb_delay();
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+ mdio_bb_set_mdc(priv, 1);
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+ mdio_bb_delay();
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+ mdio_bb_set_mdc(priv, 0);
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+ mdio_bb_delay();
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+ mdio_bb_set_mdc(priv, 1);
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+ mdio_bb_delay();
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+ /* check the turnaround bit: the PHY should drive line to zero */
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+ if (mdio_bb_get_mdio(priv) != 0) {
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+ printf("PHY didn't drive TA low\n");
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+ for (i = 0; i < 32; i++) {
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+ mdio_bb_set_mdc(priv, 0);
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+ mdio_bb_delay();
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+ mdio_bb_set_mdc(priv, 1);
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+ mdio_bb_delay();
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+ }
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+ /* There is no PHY, set value to 0xFFFF */
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+ return 0xFFFF;
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+ }
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+ mdio_bb_set_mdc(priv, 0);
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+ mdio_bb_delay();
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+ /* read 16-bits of data */
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+ for (i = 0; i < 16; i++) {
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+ mdio_bb_set_mdc(priv, 1);
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+ mdio_bb_delay();
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+ data <<= 1;
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+ data |= mdio_bb_get_mdio(priv);
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+ mdio_bb_set_mdc(priv, 0);
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+ mdio_bb_delay();
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+ }
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+
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+ mdio_bb_set_mdc(priv, 1);
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+ mdio_bb_delay();
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+ mdio_bb_set_mdc(priv, 0);
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+ mdio_bb_delay();
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+ mdio_bb_set_mdc(priv, 1);
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+ mdio_bb_delay();
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+
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+ debug("cpld_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, data);
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+
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+ return data;
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+}
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+
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+static void mdio_bb_write(struct renesas_v3msk_sysreset_priv *priv,
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+ u8 addr, u8 reg, u16 val)
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+{
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+ int i;
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+
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+ mdio_bb_pre(priv, 1, addr, reg);
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+ /* send the TA (2-bits of turn-around '10') */
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+ mdio_bb_set_mdio(priv, 1);
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+ mdio_bb_set_mdc(priv, 0);
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+ mdio_bb_delay();
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+ mdio_bb_set_mdc(priv, 1);
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+ mdio_bb_delay();
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+ mdio_bb_set_mdio(priv, 0);
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+ mdio_bb_set_mdc(priv, 0);
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+ mdio_bb_delay();
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+ mdio_bb_set_mdc(priv, 1);
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+ mdio_bb_delay();
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+ /* write 16-bits of data */
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+ for (i = 0; i < 16; i++) {
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+ mdio_bb_set_mdio(priv, val & 0x8000); /* MSB first */
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+ mdio_bb_set_mdc(priv, 0);
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+ mdio_bb_delay();
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+ mdio_bb_set_mdc(priv, 1);
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+ mdio_bb_delay();
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+ val <<= 1;
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+ }
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+ /* tri-state MDIO */
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+ mdio_bb_tristate_mdio(priv);
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+ mdio_bb_set_mdc(priv, 0);
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+ mdio_bb_delay();
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+ mdio_bb_set_mdc(priv, 1);
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+ mdio_bb_delay();
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+}
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+
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+static u16 cpld_read(struct udevice *dev, u16 addr)
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+{
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+ struct renesas_v3msk_sysreset_priv *priv = dev_get_priv(dev);
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+
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+ /* random flash reads require 2 reads: first read is unreliable */
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+ if (addr >= CPLD_ADDR_PCB_VERSION)
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+ mdio_bb_read(priv, addr >> 5, addr & 0x1f);
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+
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+ return mdio_bb_read(priv, addr >> 5, addr & 0x1f);
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+}
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+
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+static void cpld_write(struct udevice *dev, u16 addr, u16 data)
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+{
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+ struct renesas_v3msk_sysreset_priv *priv = dev_get_priv(dev);
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+
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+ mdio_bb_write(priv, addr >> 5, addr & 0x1f, data);
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+}
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+
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+static int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])
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+{
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+ struct udevice *dev;
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+ u16 addr, val;
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+ int ret;
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+
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+ ret = uclass_get_device_by_driver(UCLASS_SYSRESET,
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+ DM_DRIVER_GET(sysreset_renesas_v3msk),
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+ &dev);
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+ if (ret)
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+ return ret;
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+
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+ if (argc == 2 && strcmp(argv[1], "info") == 0) {
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+ printf("Product: 0x%08x\n",
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+ (cpld_read(dev, CPLD_ADDR_PRODUCT_H) << 16) |
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+ cpld_read(dev, CPLD_ADDR_PRODUCT_L));
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+ printf("CPLD version: 0x%08x\n",
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+ (cpld_read(dev, CPLD_ADDR_CPLD_VERSION_Y) << 16) |
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+ cpld_read(dev, CPLD_ADDR_CPLD_VERSION_D));
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+ printf("Mode setting (MD0..26): 0x%08x\n",
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+ (cpld_read(dev, CPLD_ADDR_MODE_APPLIED_H) << 16) |
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+ cpld_read(dev, CPLD_ADDR_MODE_APPLIED_L));
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+ printf("DIPSW (SW4, SW5): 0x%02x, 0x%x\n",
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+ (cpld_read(dev, CPLD_ADDR_DIPSW) & 0xff) ^ 0xff,
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+ (cpld_read(dev, CPLD_ADDR_DIPSW) >> 8) ^ 0xf);
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+ printf("Power config: 0x%08x\n",
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+ cpld_read(dev, CPLD_ADDR_POWER_CFG));
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+ printf("Periferals config: 0x%08x\n",
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+ (cpld_read(dev, CPLD_ADDR_PERI_CFG2) << 16) |
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+ cpld_read(dev, CPLD_ADDR_PERI_CFG1));
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+ printf("PCB version: %d.%d\n",
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+ cpld_read(dev, CPLD_ADDR_PCB_VERSION) >> 8,
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+ cpld_read(dev, CPLD_ADDR_PCB_VERSION) & 0xff);
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+ printf("SOC version: %d.%d\n",
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+ cpld_read(dev, CPLD_ADDR_SOC_VERSION) >> 8,
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+ cpld_read(dev, CPLD_ADDR_SOC_VERSION) & 0xff);
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+ printf("PCB S/N: %d\n",
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+ (cpld_read(dev, CPLD_ADDR_PCB_SN_H) << 16) |
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+ cpld_read(dev, CPLD_ADDR_PCB_SN_L));
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+ return 0;
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+ }
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+
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+ if (argc < 3)
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+ return CMD_RET_USAGE;
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+
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+ addr = simple_strtoul(argv[2], NULL, 16);
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+ if (!(addr >= CPLD_ADDR_PRODUCT_L && addr <= CPLD_ADDR_LEDS)) {
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+ printf("cpld invalid addr\n");
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+ return CMD_RET_USAGE;
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+ }
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+
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+ if (argc == 3 && strcmp(argv[1], "read") == 0) {
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+ printf("0x%x\n", cpld_read(dev, addr));
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+ } else if (argc == 4 && strcmp(argv[1], "write") == 0) {
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+ val = simple_strtoul(argv[3], NULL, 16);
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+ cpld_write(dev, addr, val);
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+ }
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+
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+ return 0;
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+}
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+
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+U_BOOT_CMD(cpld, 4, 1, do_cpld,
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+ "CPLD access",
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+ "info\n"
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+ "cpld read addr\n"
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+ "cpld write addr val\n"
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+);
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+
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+static int renesas_v3msk_sysreset_request(struct udevice *dev, enum sysreset_t type)
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+{
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+ cpld_write(dev, CPLD_ADDR_RESET, 1);
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+
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+ return -EINPROGRESS;
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+}
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+
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+static int renesas_v3msk_sysreset_probe(struct udevice *dev)
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+{
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+ struct renesas_v3msk_sysreset_priv *priv = dev_get_priv(dev);
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+
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+ if (gpio_request_by_name(dev, "gpio-miso", 0, &priv->miso,
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+ GPIOD_IS_IN))
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+ return -EINVAL;
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+
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+ if (gpio_request_by_name(dev, "gpio-mosi", 0, &priv->mosi,
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+ GPIOD_IS_OUT))
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+ return -EINVAL;
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+
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+ if (gpio_request_by_name(dev, "gpio-mdc", 0, &priv->mdc,
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+ GPIOD_IS_OUT))
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+ return -EINVAL;
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+
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+ if (gpio_request_by_name(dev, "gpio-enablez", 0, &priv->enablez,
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+ GPIOD_IS_OUT))
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+ return -EINVAL;
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+
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+ /* V3MSK Videobox Mini board has CANFD PHY connected
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+ * we must shutdown this chip to use bb pins
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+ */
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+ gpio_request_list_by_name(dev, "gpios", priv->gpios, CPLD_MAX_GPIOS,
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+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
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+
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+ return 0;
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+}
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+
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+static struct sysreset_ops renesas_v3msk_sysreset = {
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+ .request = renesas_v3msk_sysreset_request,
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+};
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+
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+static const struct udevice_id renesas_v3msk_sysreset_ids[] = {
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+ { .compatible = "renesas,v3msk-cpld" },
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+ { /* sentinel */ }
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+};
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+
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+U_BOOT_DRIVER(sysreset_renesas_v3msk) = {
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+ .name = "renesas_v3msk_sysreset",
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+ .id = UCLASS_SYSRESET,
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+ .ops = &renesas_v3msk_sysreset,
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+ .probe = renesas_v3msk_sysreset_probe,
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+ .of_match = renesas_v3msk_sysreset_ids,
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+ .priv_auto = sizeof(struct renesas_v3msk_sysreset_priv),
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+};
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