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@@ -0,0 +1,306 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Copyright 2018-2019 NXP
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+ *
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+ * Peng Fan <peng.fan@nxp.com>
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+ */
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+
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+#include <common.h>
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+#include <asm/arch/clock.h>
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+#include <asm/arch/imx-regs.h>
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+#include <asm/arch/sys_proto.h>
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+#include <asm/io.h>
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+#include <clk.h>
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+#include <clk-uclass.h>
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+#include <dt-bindings/clock/imx8mm-clock.h>
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+#include <div64.h>
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+#include <errno.h>
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+
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+DECLARE_GLOBAL_DATA_PTR;
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+
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+static struct anamix_pll *ana_pll = (struct anamix_pll *)ANATOP_BASE_ADDR;
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+
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+void enable_ocotp_clk(unsigned char enable)
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+{
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+ struct clk *clkp;
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+ int ret;
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+
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+ ret = clk_get_by_id(IMX8MM_CLK_OCOTP_ROOT, &clkp);
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+ if (ret) {
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+ printf("%s: err: %d\n", __func__, ret);
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+ return;
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+ }
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+
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+ enable ? clk_enable(clkp) : clk_disable(clkp);
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+}
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+
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+int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
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+{
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+ struct clk *clkp;
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+ int ret;
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+
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+ ret = clk_get_by_id(IMX8MM_CLK_I2C1_ROOT + i2c_num, &clkp);
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+ if (ret) {
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+ printf("%s: err: %d\n", __func__, ret);
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+ return ret;
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+ }
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+
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+ return enable ? clk_enable(clkp) : clk_disable(clkp);
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+}
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+
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+#ifdef CONFIG_SPL_BUILD
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+static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
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+ PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
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+ PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
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+ PLL_1443X_RATE(650000000U, 325, 3, 2, 0),
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+ PLL_1443X_RATE(600000000U, 300, 3, 2, 0),
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+ PLL_1443X_RATE(594000000U, 99, 1, 2, 0),
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+ PLL_1443X_RATE(400000000U, 300, 9, 1, 0),
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+ PLL_1443X_RATE(266666667U, 400, 9, 2, 0),
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+ PLL_1443X_RATE(167000000U, 334, 3, 4, 0),
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+ PLL_1443X_RATE(100000000U, 300, 9, 3, 0),
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+};
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+
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+int fracpll_configure(enum pll_clocks pll, u32 freq)
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+{
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+ int i;
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+ u32 tmp, div_val;
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+ void *pll_base;
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+ struct imx_int_pll_rate_table *rate;
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+
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+ for (i = 0; i < ARRAY_SIZE(imx8mm_fracpll_tbl); i++) {
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+ if (freq == imx8mm_fracpll_tbl[i].rate)
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+ break;
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+ }
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+
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+ if (i == ARRAY_SIZE(imx8mm_fracpll_tbl)) {
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+ printf("No matched freq table %u\n", freq);
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+ return -EINVAL;
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+ }
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+
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+ rate = &imx8mm_fracpll_tbl[i];
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+
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+ switch (pll) {
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+ case ANATOP_DRAM_PLL:
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+ setbits_le32(GPC_BASE_ADDR + 0xEC, 1 << 7);
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+ setbits_le32(GPC_BASE_ADDR + 0xF8, 1 << 5);
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+ writel(SRC_DDR1_ENABLE_MASK, SRC_BASE_ADDR + 0x1004);
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+
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+ pll_base = &ana_pll->dram_pll_gnrl_ctl;
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+ break;
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+ case ANATOP_VIDEO_PLL:
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+ pll_base = &ana_pll->video_pll1_gnrl_ctl;
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+ break;
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+ default:
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+ return 0;
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+ }
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+ /* Bypass clock and set lock to pll output lock */
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+ tmp = readl(pll_base);
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+ tmp |= BYPASS_MASK;
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+ writel(tmp, pll_base);
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+
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+ /* Enable RST */
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+ tmp &= ~RST_MASK;
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+ writel(tmp, pll_base);
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+
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+ div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) |
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+ (rate->sdiv << SDIV_SHIFT);
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+ writel(div_val, pll_base + 4);
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+ writel(rate->kdiv << KDIV_SHIFT, pll_base + 8);
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+
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+ __udelay(100);
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+
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+ /* Disable RST */
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+ tmp |= RST_MASK;
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+ writel(tmp, pll_base);
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+
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+ /* Wait Lock*/
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+ while (!(readl(pll_base) & LOCK_STATUS))
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+ ;
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+
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+ /* Bypass */
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+ tmp &= ~BYPASS_MASK;
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+ writel(tmp, pll_base);
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+
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+ return 0;
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+}
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+
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+void dram_pll_init(ulong pll_val)
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+{
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+ fracpll_configure(ANATOP_DRAM_PLL, pll_val);
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+}
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+
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+static struct dram_bypass_clk_setting imx8mm_dram_bypass_tbl[] = {
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+ DRAM_BYPASS_ROOT_CONFIG(MHZ(100), 2, CLK_ROOT_PRE_DIV1, 2,
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+ CLK_ROOT_PRE_DIV2),
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+ DRAM_BYPASS_ROOT_CONFIG(MHZ(250), 3, CLK_ROOT_PRE_DIV2, 2,
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+ CLK_ROOT_PRE_DIV2),
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+ DRAM_BYPASS_ROOT_CONFIG(MHZ(400), 1, CLK_ROOT_PRE_DIV2, 3,
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+ CLK_ROOT_PRE_DIV2),
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+};
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+
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+void dram_enable_bypass(ulong clk_val)
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+{
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+ int i;
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+ struct dram_bypass_clk_setting *config;
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+
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+ for (i = 0; i < ARRAY_SIZE(imx8mm_dram_bypass_tbl); i++) {
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+ if (clk_val == imx8mm_dram_bypass_tbl[i].clk)
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+ break;
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+ }
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+
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+ if (i == ARRAY_SIZE(imx8mm_dram_bypass_tbl)) {
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+ printf("No matched freq table %lu\n", clk_val);
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+ return;
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+ }
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+
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+ config = &imx8mm_dram_bypass_tbl[i];
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+
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+ clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
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+ CLK_ROOT_SOURCE_SEL(config->alt_root_sel) |
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+ CLK_ROOT_PRE_DIV(config->alt_pre_div));
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+ clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
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+ CLK_ROOT_SOURCE_SEL(config->apb_root_sel) |
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+ CLK_ROOT_PRE_DIV(config->apb_pre_div));
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+ clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
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+ CLK_ROOT_SOURCE_SEL(1));
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+}
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+
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+void dram_disable_bypass(void)
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+{
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+ clock_set_target_val(DRAM_SEL_CFG, CLK_ROOT_ON |
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+ CLK_ROOT_SOURCE_SEL(0));
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+ clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
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+ CLK_ROOT_SOURCE_SEL(4) |
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+ CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV5));
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+}
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+#endif
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+
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+void init_uart_clk(u32 index)
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+{
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+ /*
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+ * set uart clock root
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+ * 24M OSC
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+ */
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+ switch (index) {
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+ case 0:
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+ clock_enable(CCGR_UART1, 0);
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+ clock_set_target_val(UART1_CLK_ROOT, CLK_ROOT_ON |
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+ CLK_ROOT_SOURCE_SEL(0));
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+ clock_enable(CCGR_UART1, 1);
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+ return;
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+ case 1:
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+ clock_enable(CCGR_UART2, 0);
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+ clock_set_target_val(UART2_CLK_ROOT, CLK_ROOT_ON |
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+ CLK_ROOT_SOURCE_SEL(0));
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+ clock_enable(CCGR_UART2, 1);
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+ return;
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+ case 2:
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+ clock_enable(CCGR_UART3, 0);
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+ clock_set_target_val(UART3_CLK_ROOT, CLK_ROOT_ON |
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+ CLK_ROOT_SOURCE_SEL(0));
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+ clock_enable(CCGR_UART3, 1);
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+ return;
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+ case 3:
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+ clock_enable(CCGR_UART4, 0);
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+ clock_set_target_val(UART4_CLK_ROOT, CLK_ROOT_ON |
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+ CLK_ROOT_SOURCE_SEL(0));
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+ clock_enable(CCGR_UART4, 1);
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+ return;
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+ default:
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+ printf("Invalid uart index\n");
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+ return;
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+ }
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+}
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+
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+void init_wdog_clk(void)
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+{
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+ clock_enable(CCGR_WDOG1, 0);
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+ clock_enable(CCGR_WDOG2, 0);
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+ clock_enable(CCGR_WDOG3, 0);
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+ clock_set_target_val(WDOG_CLK_ROOT, CLK_ROOT_ON |
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+ CLK_ROOT_SOURCE_SEL(0));
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+ clock_enable(CCGR_WDOG1, 1);
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+ clock_enable(CCGR_WDOG2, 1);
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+ clock_enable(CCGR_WDOG3, 1);
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+}
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+
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+int clock_init(void)
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+{
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+ u32 val_cfg0;
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+
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+ /*
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+ * The gate is not exported to clk tree, so configure them here.
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+ * According to ANAMIX SPEC
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+ * sys pll1 fixed at 800MHz
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+ * sys pll2 fixed at 1GHz
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+ * Here we only enable the outputs.
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+ */
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+ val_cfg0 = readl(&ana_pll->sys_pll1_gnrl_ctl);
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+ val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
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+ INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
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+ INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
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+ INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
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+ INTPLL_DIV20_CLKE_MASK;
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+ writel(val_cfg0, &ana_pll->sys_pll1_gnrl_ctl);
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+
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+ val_cfg0 = readl(&ana_pll->sys_pll2_gnrl_ctl);
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+ val_cfg0 |= INTPLL_CLKE_MASK | INTPLL_DIV2_CLKE_MASK |
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+ INTPLL_DIV3_CLKE_MASK | INTPLL_DIV4_CLKE_MASK |
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+ INTPLL_DIV5_CLKE_MASK | INTPLL_DIV6_CLKE_MASK |
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+ INTPLL_DIV8_CLKE_MASK | INTPLL_DIV10_CLKE_MASK |
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+ INTPLL_DIV20_CLKE_MASK;
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+ writel(val_cfg0, &ana_pll->sys_pll2_gnrl_ctl);
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+
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+ /* config GIC to sys_pll2_100m */
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+ clock_enable(CCGR_GIC, 0);
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+ clock_set_target_val(GIC_CLK_ROOT, CLK_ROOT_ON |
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+ CLK_ROOT_SOURCE_SEL(3));
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+ clock_enable(CCGR_GIC, 1);
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+
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+ clock_set_target_val(NAND_USDHC_BUS_CLK_ROOT, CLK_ROOT_ON |
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+ CLK_ROOT_SOURCE_SEL(1));
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+
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+ clock_enable(CCGR_DDR1, 0);
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+ clock_set_target_val(DRAM_ALT_CLK_ROOT, CLK_ROOT_ON |
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+ CLK_ROOT_SOURCE_SEL(1));
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+ clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
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+ CLK_ROOT_SOURCE_SEL(1));
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+ clock_enable(CCGR_DDR1, 1);
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+
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+ init_wdog_clk();
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+
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+ clock_enable(CCGR_TEMP_SENSOR, 1);
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+
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+ clock_enable(CCGR_SEC_DEBUG, 1);
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+
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+ return 0;
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+};
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+
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+u32 imx_get_uartclk(void)
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+{
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+ return 24000000U;
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+}
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+
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+u32 mxc_get_clock(enum mxc_clock clk)
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+{
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+ struct clk *clkp;
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+ int ret;
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+
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+ switch (clk) {
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+ case MXC_IPG_CLK:
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+ ret = clk_get_by_id(IMX8MM_CLK_IPG_ROOT, &clkp);
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+ if (ret)
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+ return 0;
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+ return clk_get_rate(clkp);
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+ case MXC_ARM_CLK:
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+ ret = clk_get_by_id(IMX8MM_CLK_A53_DIV, &clkp);
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+ if (ret)
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+ return 0;
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+ return clk_get_rate(clkp);
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+ default:
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+ printf("%s: %d not supported\n", __func__, clk);
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+ }
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+
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+ return 0;
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+}
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