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@@ -46,7 +46,8 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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-#include <dt-bindings/pinctrl/sun4i-a10.h>
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+#include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
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+#include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
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/ {
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interrupt-parent = <&gic>;
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@@ -60,7 +61,9 @@
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compatible = "allwinner,simple-framebuffer",
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"simple-framebuffer";
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allwinner,pipeline = "de_be0-lcd0";
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- clocks = <&pll6 0>;
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+ clocks = <&ccu CLK_BUS_LCD>, <&ccu CLK_BUS_DE_BE>,
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+ <&ccu CLK_LCD_CH0>, <&ccu CLK_DE_BE>,
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+ <&ccu CLK_DRAM_DE_BE>, <&ccu CLK_DRC>;
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status = "disabled";
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};
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};
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@@ -80,7 +83,7 @@
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#address-cells = <1>;
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#size-cells = <0>;
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- cpu@0 {
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+ cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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@@ -102,151 +105,16 @@
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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+ clock-accuracy = <50000>;
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clock-output-names = "osc24M";
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};
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- osc32k: osc32k_clk {
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+ ext_osc32k: ext_osc32k_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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- clock-output-names = "osc32k";
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- };
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-
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- pll1: clk@01c20000 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun8i-a23-pll1-clk";
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- reg = <0x01c20000 0x4>;
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- clocks = <&osc24M>;
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- clock-output-names = "pll1";
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- };
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-
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- /* dummy clock until actually implemented */
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- pll5: pll5_clk {
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- #clock-cells = <0>;
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- compatible = "fixed-clock";
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- clock-frequency = <0>;
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- clock-output-names = "pll5";
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- };
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-
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- pll6: clk@01c20028 {
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- #clock-cells = <1>;
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- compatible = "allwinner,sun6i-a31-pll6-clk";
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- reg = <0x01c20028 0x4>;
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- clocks = <&osc24M>;
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- clock-output-names = "pll6", "pll6x2";
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- };
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-
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- cpu: cpu_clk@01c20050 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun4i-a10-cpu-clk";
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- reg = <0x01c20050 0x4>;
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-
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- /*
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- * PLL1 is listed twice here.
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- * While it looks suspicious, it's actually documented
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- * that way both in the datasheet and in the code from
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- * Allwinner.
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- */
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- clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
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- clock-output-names = "cpu";
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- };
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-
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- axi: axi_clk@01c20050 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun8i-a23-axi-clk";
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- reg = <0x01c20050 0x4>;
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- clocks = <&cpu>;
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- clock-output-names = "axi";
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- };
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-
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- ahb1: ahb1_clk@01c20054 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun6i-a31-ahb1-clk";
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- reg = <0x01c20054 0x4>;
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- clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
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- clock-output-names = "ahb1";
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- };
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-
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- apb1: apb1_clk@01c20054 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun4i-a10-apb0-clk";
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- reg = <0x01c20054 0x4>;
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- clocks = <&ahb1>;
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- clock-output-names = "apb1";
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- };
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-
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- apb1_gates: clk@01c20068 {
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- #clock-cells = <1>;
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- compatible = "allwinner,sun8i-a23-apb1-gates-clk";
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- reg = <0x01c20068 0x4>;
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- clocks = <&apb1>;
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- clock-indices = <0>, <5>,
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- <12>, <13>;
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- clock-output-names = "apb1_codec", "apb1_pio",
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- "apb1_daudio0", "apb1_daudio1";
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- };
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-
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- apb2: clk@01c20058 {
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- #clock-cells = <0>;
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- compatible = "allwinner,sun4i-a10-apb1-clk";
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- reg = <0x01c20058 0x4>;
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- clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
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- clock-output-names = "apb2";
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- };
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-
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- apb2_gates: clk@01c2006c {
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- #clock-cells = <1>;
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- compatible = "allwinner,sun8i-a23-apb2-gates-clk";
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- reg = <0x01c2006c 0x4>;
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- clocks = <&apb2>;
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- clock-indices = <0>, <1>,
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- <2>, <16>,
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- <17>, <18>,
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- <19>, <20>;
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- clock-output-names = "apb2_i2c0", "apb2_i2c1",
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- "apb2_i2c2", "apb2_uart0",
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- "apb2_uart1", "apb2_uart2",
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- "apb2_uart3", "apb2_uart4";
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- };
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-
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- mmc0_clk: clk@01c20088 {
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- #clock-cells = <1>;
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- compatible = "allwinner,sun4i-a10-mmc-clk";
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- reg = <0x01c20088 0x4>;
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- clocks = <&osc24M>, <&pll6 0>;
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- clock-output-names = "mmc0",
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- "mmc0_output",
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- "mmc0_sample";
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- };
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-
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- mmc1_clk: clk@01c2008c {
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- #clock-cells = <1>;
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- compatible = "allwinner,sun4i-a10-mmc-clk";
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- reg = <0x01c2008c 0x4>;
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- clocks = <&osc24M>, <&pll6 0>;
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- clock-output-names = "mmc1",
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- "mmc1_output",
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- "mmc1_sample";
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- };
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-
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- mmc2_clk: clk@01c20090 {
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- #clock-cells = <1>;
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- compatible = "allwinner,sun4i-a10-mmc-clk";
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- reg = <0x01c20090 0x4>;
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- clocks = <&osc24M>, <&pll6 0>;
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- clock-output-names = "mmc2",
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- "mmc2_output",
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- "mmc2_sample";
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- };
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-
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- usb_clk: clk@01c200cc {
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- #clock-cells = <1>;
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- #reset-cells = <1>;
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- compatible = "allwinner,sun8i-a23-usb-clk";
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- reg = <0x01c200cc 0x4>;
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- clocks = <&osc24M>;
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- clock-output-names = "usb_phy0", "usb_phy1", "usb_hsic",
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- "usb_hsic_12M", "usb_ohci0";
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+ clock-accuracy = <50000>;
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+ clock-output-names = "ext-osc32k";
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};
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};
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@@ -260,24 +128,23 @@
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compatible = "allwinner,sun8i-a23-dma";
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reg = <0x01c02000 0x1000>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&ahb1_gates 6>;
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- resets = <&ahb1_rst 6>;
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+ clocks = <&ccu CLK_BUS_DMA>;
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+ resets = <&ccu RST_BUS_DMA>;
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#dma-cells = <1>;
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};
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mmc0: mmc@01c0f000 {
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- compatible = "allwinner,sun7i-a20-mmc",
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- "allwinner,sun5i-a13-mmc";
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+ compatible = "allwinner,sun7i-a20-mmc";
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reg = <0x01c0f000 0x1000>;
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- clocks = <&ahb1_gates 8>,
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- <&mmc0_clk 0>,
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- <&mmc0_clk 1>,
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- <&mmc0_clk 2>;
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+ clocks = <&ccu CLK_BUS_MMC0>,
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+ <&ccu CLK_MMC0>,
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+ <&ccu CLK_MMC0_OUTPUT>,
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+ <&ccu CLK_MMC0_SAMPLE>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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- resets = <&ahb1_rst 8>;
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+ resets = <&ccu RST_BUS_MMC0>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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@@ -286,18 +153,17 @@
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};
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mmc1: mmc@01c10000 {
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- compatible = "allwinner,sun7i-a20-mmc",
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- "allwinner,sun5i-a13-mmc";
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+ compatible = "allwinner,sun7i-a20-mmc";
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reg = <0x01c10000 0x1000>;
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- clocks = <&ahb1_gates 9>,
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- <&mmc1_clk 0>,
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- <&mmc1_clk 1>,
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- <&mmc1_clk 2>;
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+ clocks = <&ccu CLK_BUS_MMC1>,
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+ <&ccu CLK_MMC1>,
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+ <&ccu CLK_MMC1_OUTPUT>,
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+ <&ccu CLK_MMC1_SAMPLE>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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- resets = <&ahb1_rst 9>;
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+ resets = <&ccu RST_BUS_MMC1>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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@@ -306,18 +172,17 @@
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};
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mmc2: mmc@01c11000 {
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- compatible = "allwinner,sun7i-a20-mmc",
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- "allwinner,sun5i-a13-mmc";
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+ compatible = "allwinner,sun7i-a20-mmc";
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reg = <0x01c11000 0x1000>;
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- clocks = <&ahb1_gates 10>,
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- <&mmc2_clk 0>,
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- <&mmc2_clk 1>,
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- <&mmc2_clk 2>;
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+ clocks = <&ccu CLK_BUS_MMC2>,
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+ <&ccu CLK_MMC2>,
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+ <&ccu CLK_MMC2_OUTPUT>,
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+ <&ccu CLK_MMC2_SAMPLE>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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- resets = <&ahb1_rst 10>;
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+ resets = <&ccu RST_BUS_MMC2>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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@@ -325,12 +190,55 @@
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#size-cells = <0>;
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};
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+ nfc: nand@01c03000 {
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+ compatible = "allwinner,sun4i-a10-nand";
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+ reg = <0x01c03000 0x1000>;
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+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND>;
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+ clock-names = "ahb", "mod";
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+ resets = <&ccu RST_BUS_NAND>;
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+ reset-names = "ahb";
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ };
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+
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+ usb_otg: usb@01c19000 {
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+ /* compatible gets set in SoC specific dtsi file */
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+ reg = <0x01c19000 0x0400>;
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+ clocks = <&ccu CLK_BUS_OTG>;
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+ resets = <&ccu RST_BUS_OTG>;
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+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "mc";
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+ phys = <&usbphy 0>;
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+ phy-names = "usb";
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+ extcon = <&usbphy 0>;
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+ status = "disabled";
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+ };
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+
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+ usbphy: phy@01c19400 {
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+ /*
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+ * compatible and address regions get set in
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+ * SoC specific dtsi file
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+ */
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+ clocks = <&ccu CLK_USB_PHY0>,
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+ <&ccu CLK_USB_PHY1>;
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+ clock-names = "usb0_phy",
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+ "usb1_phy";
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+ resets = <&ccu RST_USB_PHY0>,
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+ <&ccu RST_USB_PHY1>;
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+ reset-names = "usb0_reset",
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+ "usb1_reset";
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+ status = "disabled";
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+ #phy-cells = <1>;
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+ };
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+
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ehci0: usb@01c1a000 {
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compatible = "allwinner,sun8i-a23-ehci", "generic-ehci";
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reg = <0x01c1a000 0x100>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&ahb1_gates 26>;
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- resets = <&ahb1_rst 26>;
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+ clocks = <&ccu CLK_BUS_EHCI>;
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+ resets = <&ccu RST_BUS_EHCI>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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@@ -340,101 +248,100 @@
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compatible = "allwinner,sun8i-a23-ohci", "generic-ohci";
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reg = <0x01c1a400 0x100>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&ahb1_gates 29>, <&usb_clk 16>;
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- resets = <&ahb1_rst 29>;
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+ clocks = <&ccu CLK_BUS_OHCI>, <&ccu CLK_USB_OHCI>;
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+ resets = <&ccu RST_BUS_OHCI>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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+ ccu: clock@01c20000 {
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+ reg = <0x01c20000 0x400>;
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+ clocks = <&osc24M>, <&rtc 0>;
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+ clock-names = "hosc", "losc";
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+ #clock-cells = <1>;
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+ #reset-cells = <1>;
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+ };
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+
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pio: pinctrl@01c20800 {
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/* compatible gets set in SoC specific dtsi file */
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reg = <0x01c20800 0x400>;
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/* interrupts get set in SoC specific dtsi file */
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- clocks = <&apb1_gates 5>;
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+ clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>;
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+ clock-names = "apb", "hosc", "losc";
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <3>;
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#gpio-cells = <3>;
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uart0_pins_a: uart0@0 {
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- allwinner,pins = "PF2", "PF4";
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- allwinner,function = "uart0";
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- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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+ pins = "PF2", "PF4";
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+ function = "uart0";
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+ };
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+
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+ uart1_pins_a: uart1@0 {
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+ pins = "PG6", "PG7";
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+ function = "uart1";
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+ };
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+
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+ uart1_pins_cts_rts_a: uart1-cts-rts@0 {
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+ pins = "PG8", "PG9";
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+ function = "uart1";
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};
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mmc0_pins_a: mmc0@0 {
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- allwinner,pins = "PF0", "PF1", "PF2",
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- "PF3", "PF4", "PF5";
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- allwinner,function = "mmc0";
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- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
+ pins = "PF0", "PF1", "PF2",
|
|
|
+ "PF3", "PF4", "PF5";
|
|
|
+ function = "mmc0";
|
|
|
+ drive-strength = <30>;
|
|
|
+ bias-pull-up;
|
|
|
};
|
|
|
|
|
|
mmc1_pins_a: mmc1@0 {
|
|
|
- allwinner,pins = "PG0", "PG1", "PG2",
|
|
|
- "PG3", "PG4", "PG5";
|
|
|
- allwinner,function = "mmc1";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
+ pins = "PG0", "PG1", "PG2",
|
|
|
+ "PG3", "PG4", "PG5";
|
|
|
+ function = "mmc1";
|
|
|
+ drive-strength = <30>;
|
|
|
+ bias-pull-up;
|
|
|
};
|
|
|
|
|
|
mmc2_8bit_pins: mmc2_8bit {
|
|
|
- allwinner,pins = "PC5", "PC6", "PC8",
|
|
|
- "PC9", "PC10", "PC11",
|
|
|
- "PC12", "PC13", "PC14",
|
|
|
- "PC15", "PC16";
|
|
|
- allwinner,function = "mmc2";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
+ pins = "PC5", "PC6", "PC8",
|
|
|
+ "PC9", "PC10", "PC11",
|
|
|
+ "PC12", "PC13", "PC14",
|
|
|
+ "PC15", "PC16";
|
|
|
+ function = "mmc2";
|
|
|
+ drive-strength = <30>;
|
|
|
+ bias-pull-up;
|
|
|
};
|
|
|
|
|
|
pwm0_pins: pwm0 {
|
|
|
- allwinner,pins = "PH0";
|
|
|
- allwinner,function = "pwm0";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
+ pins = "PH0";
|
|
|
+ function = "pwm0";
|
|
|
};
|
|
|
|
|
|
i2c0_pins_a: i2c0@0 {
|
|
|
- allwinner,pins = "PH2", "PH3";
|
|
|
- allwinner,function = "i2c0";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
+ pins = "PH2", "PH3";
|
|
|
+ function = "i2c0";
|
|
|
};
|
|
|
|
|
|
i2c1_pins_a: i2c1@0 {
|
|
|
- allwinner,pins = "PH4", "PH5";
|
|
|
- allwinner,function = "i2c1";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
+ pins = "PH4", "PH5";
|
|
|
+ function = "i2c1";
|
|
|
};
|
|
|
|
|
|
i2c2_pins_a: i2c2@0 {
|
|
|
- allwinner,pins = "PE12", "PE13";
|
|
|
- allwinner,function = "i2c2";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
+ pins = "PE12", "PE13";
|
|
|
+ function = "i2c2";
|
|
|
};
|
|
|
- };
|
|
|
-
|
|
|
- ahb1_rst: reset@01c202c0 {
|
|
|
- #reset-cells = <1>;
|
|
|
- compatible = "allwinner,sun6i-a31-clock-reset";
|
|
|
- reg = <0x01c202c0 0xc>;
|
|
|
- };
|
|
|
|
|
|
- apb1_rst: reset@01c202d0 {
|
|
|
- #reset-cells = <1>;
|
|
|
- compatible = "allwinner,sun6i-a31-clock-reset";
|
|
|
- reg = <0x01c202d0 0x4>;
|
|
|
- };
|
|
|
-
|
|
|
- apb2_rst: reset@01c202d8 {
|
|
|
- #reset-cells = <1>;
|
|
|
- compatible = "allwinner,sun6i-a31-clock-reset";
|
|
|
- reg = <0x01c202d8 0x4>;
|
|
|
+ lcd_rgb666_pins: lcd-rgb666@0 {
|
|
|
+ pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
|
|
|
+ "PD10", "PD11", "PD12", "PD13", "PD14", "PD15",
|
|
|
+ "PD18", "PD19", "PD20", "PD21", "PD22", "PD23",
|
|
|
+ "PD24", "PD25", "PD26", "PD27";
|
|
|
+ function = "lcd0";
|
|
|
+ };
|
|
|
};
|
|
|
|
|
|
timer@01c20c00 {
|
|
@@ -472,8 +379,8 @@
|
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
reg-shift = <2>;
|
|
|
reg-io-width = <4>;
|
|
|
- clocks = <&apb2_gates 16>;
|
|
|
- resets = <&apb2_rst 16>;
|
|
|
+ clocks = <&ccu CLK_BUS_UART0>;
|
|
|
+ resets = <&ccu RST_BUS_UART0>;
|
|
|
dmas = <&dma 6>, <&dma 6>;
|
|
|
dma-names = "rx", "tx";
|
|
|
status = "disabled";
|
|
@@ -485,8 +392,8 @@
|
|
|
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
reg-shift = <2>;
|
|
|
reg-io-width = <4>;
|
|
|
- clocks = <&apb2_gates 17>;
|
|
|
- resets = <&apb2_rst 17>;
|
|
|
+ clocks = <&ccu CLK_BUS_UART1>;
|
|
|
+ resets = <&ccu RST_BUS_UART1>;
|
|
|
dmas = <&dma 7>, <&dma 7>;
|
|
|
dma-names = "rx", "tx";
|
|
|
status = "disabled";
|
|
@@ -498,8 +405,8 @@
|
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
reg-shift = <2>;
|
|
|
reg-io-width = <4>;
|
|
|
- clocks = <&apb2_gates 18>;
|
|
|
- resets = <&apb2_rst 18>;
|
|
|
+ clocks = <&ccu CLK_BUS_UART2>;
|
|
|
+ resets = <&ccu RST_BUS_UART2>;
|
|
|
dmas = <&dma 8>, <&dma 8>;
|
|
|
dma-names = "rx", "tx";
|
|
|
status = "disabled";
|
|
@@ -511,8 +418,8 @@
|
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
reg-shift = <2>;
|
|
|
reg-io-width = <4>;
|
|
|
- clocks = <&apb2_gates 19>;
|
|
|
- resets = <&apb2_rst 19>;
|
|
|
+ clocks = <&ccu CLK_BUS_UART3>;
|
|
|
+ resets = <&ccu RST_BUS_UART3>;
|
|
|
dmas = <&dma 9>, <&dma 9>;
|
|
|
dma-names = "rx", "tx";
|
|
|
status = "disabled";
|
|
@@ -524,8 +431,8 @@
|
|
|
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
reg-shift = <2>;
|
|
|
reg-io-width = <4>;
|
|
|
- clocks = <&apb2_gates 20>;
|
|
|
- resets = <&apb2_rst 20>;
|
|
|
+ clocks = <&ccu CLK_BUS_UART4>;
|
|
|
+ resets = <&ccu RST_BUS_UART4>;
|
|
|
dmas = <&dma 10>, <&dma 10>;
|
|
|
dma-names = "rx", "tx";
|
|
|
status = "disabled";
|
|
@@ -535,8 +442,8 @@
|
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
|
reg = <0x01c2ac00 0x400>;
|
|
|
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
- clocks = <&apb2_gates 0>;
|
|
|
- resets = <&apb2_rst 0>;
|
|
|
+ clocks = <&ccu CLK_BUS_I2C0>;
|
|
|
+ resets = <&ccu RST_BUS_I2C0>;
|
|
|
status = "disabled";
|
|
|
#address-cells = <1>;
|
|
|
#size-cells = <0>;
|
|
@@ -546,8 +453,8 @@
|
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
|
reg = <0x01c2b000 0x400>;
|
|
|
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
- clocks = <&apb2_gates 1>;
|
|
|
- resets = <&apb2_rst 1>;
|
|
|
+ clocks = <&ccu CLK_BUS_I2C1>;
|
|
|
+ resets = <&ccu RST_BUS_I2C1>;
|
|
|
status = "disabled";
|
|
|
#address-cells = <1>;
|
|
|
#size-cells = <0>;
|
|
@@ -557,17 +464,44 @@
|
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
|
|
reg = <0x01c2b400 0x400>;
|
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
- clocks = <&apb2_gates 2>;
|
|
|
- resets = <&apb2_rst 2>;
|
|
|
+ clocks = <&ccu CLK_BUS_I2C2>;
|
|
|
+ resets = <&ccu RST_BUS_I2C2>;
|
|
|
status = "disabled";
|
|
|
#address-cells = <1>;
|
|
|
#size-cells = <0>;
|
|
|
};
|
|
|
|
|
|
+ mali: gpu@1c40000 {
|
|
|
+ compatible = "allwinner,sun8i-a23-mali",
|
|
|
+ "allwinner,sun7i-a20-mali", "arm,mali-400";
|
|
|
+ reg = <0x01c40000 0x10000>;
|
|
|
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ interrupt-names = "gp",
|
|
|
+ "gpmmu",
|
|
|
+ "pp0",
|
|
|
+ "ppmmu0",
|
|
|
+ "pp1",
|
|
|
+ "ppmmu1",
|
|
|
+ "pmu";
|
|
|
+ clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
|
|
|
+ clock-names = "bus", "core";
|
|
|
+ resets = <&ccu RST_BUS_GPU>;
|
|
|
+ #cooling-cells = <2>;
|
|
|
+
|
|
|
+ assigned-clocks = <&ccu CLK_GPU>;
|
|
|
+ assigned-clock-rates = <384000000>;
|
|
|
+ };
|
|
|
+
|
|
|
gic: interrupt-controller@01c81000 {
|
|
|
compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
|
|
|
reg = <0x01c81000 0x1000>,
|
|
|
- <0x01c82000 0x1000>,
|
|
|
+ <0x01c82000 0x2000>,
|
|
|
<0x01c84000 0x2000>,
|
|
|
<0x01c86000 0x2000>;
|
|
|
interrupt-controller;
|
|
@@ -580,13 +514,16 @@
|
|
|
reg = <0x01f00000 0x54>;
|
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clock-output-names = "osc32k";
|
|
|
+ clocks = <&ext_osc32k>;
|
|
|
+ #clock-cells = <1>;
|
|
|
};
|
|
|
|
|
|
- nmi_intc: interrupt-controller@01f00c0c {
|
|
|
- compatible = "allwinner,sun6i-a31-sc-nmi";
|
|
|
+ nmi_intc: interrupt-controller@1f00c00 {
|
|
|
+ compatible = "allwinner,sun6i-a31-r-intc";
|
|
|
interrupt-controller;
|
|
|
#interrupt-cells = <2>;
|
|
|
- reg = <0x01f00c0c 0x38>;
|
|
|
+ reg = <0x01f00c00 0x400>;
|
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
};
|
|
|
|
|
@@ -632,6 +569,10 @@
|
|
|
compatible = "allwinner,sun6i-a31-clock-reset";
|
|
|
#reset-cells = <1>;
|
|
|
};
|
|
|
+
|
|
|
+ codec_analog: codec-analog {
|
|
|
+ compatible = "allwinner,sun8i-a23-codec-analog";
|
|
|
+ };
|
|
|
};
|
|
|
|
|
|
cpucfg@01f01c00 {
|
|
@@ -654,7 +595,8 @@
|
|
|
compatible = "allwinner,sun8i-a23-r-pinctrl";
|
|
|
reg = <0x01f02c00 0x400>;
|
|
|
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
- clocks = <&apb0_gates 0>;
|
|
|
+ clocks = <&apb0_gates 0>, <&osc24M>, <&rtc 0>;
|
|
|
+ clock-names = "apb", "hosc", "losc";
|
|
|
resets = <&apb0_rst 0>;
|
|
|
gpio-controller;
|
|
|
interrupt-controller;
|
|
@@ -664,17 +606,15 @@
|
|
|
#gpio-cells = <3>;
|
|
|
|
|
|
r_rsb_pins: r_rsb {
|
|
|
- allwinner,pins = "PL0", "PL1";
|
|
|
- allwinner,function = "s_rsb";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_20_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
|
|
|
+ pins = "PL0", "PL1";
|
|
|
+ function = "s_rsb";
|
|
|
+ drive-strength = <20>;
|
|
|
+ bias-pull-up;
|
|
|
};
|
|
|
|
|
|
r_uart_pins_a: r_uart@0 {
|
|
|
- allwinner,pins = "PL2", "PL3";
|
|
|
- allwinner,function = "s_uart";
|
|
|
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
|
|
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
|
|
+ pins = "PL2", "PL3";
|
|
|
+ function = "s_uart";
|
|
|
};
|
|
|
};
|
|
|
|