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@@ -501,7 +501,6 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
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struct fsl_esdhc *regs = priv->esdhc_regs;
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int div = 1;
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int pre_div = 2;
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- int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
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unsigned int sdhc_clk = priv->sdhc_clk;
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u32 time_out;
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u32 value;
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@@ -510,10 +509,10 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
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if (clock < mmc->cfg->f_min)
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clock = mmc->cfg->f_min;
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- while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
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+ while (sdhc_clk / (16 * pre_div) > clock && pre_div < 256)
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pre_div *= 2;
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- while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
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+ while (sdhc_clk / (div * pre_div) > clock && div < 16)
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div++;
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pre_div >>= 1;
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@@ -773,9 +772,6 @@ static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
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cfg->host_caps = MMC_MODE_4BIT;
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cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
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-#ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
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- cfg->host_caps |= MMC_MODE_DDR_52MHz;
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-#endif
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if (priv->bus_width > 0) {
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if (priv->bus_width < 8)
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