|
@@ -113,7 +113,7 @@
|
|
|
BR_MS_GPCM | /* MSEL = GPCM */ \
|
|
|
BR_V)
|
|
|
|
|
|
-#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
|
|
|
+#define CONFIG_SYS_OR0_PRELIM (OR_AM_256MB | \
|
|
|
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
|
|
|
OR_GPCM_SCY_5 | \
|
|
|
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
|
|
@@ -130,7 +130,7 @@
|
|
|
BR_PS_8 | /* 8 bit port size */ \
|
|
|
BR_MS_GPCM | /* MSEL = GPCM */ \
|
|
|
BR_V)
|
|
|
-#define CONFIG_SYS_OR1_PRELIM (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
|
|
|
+#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | \
|
|
|
OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
|
|
|
OR_GPCM_SCY_2 | \
|
|
|
OR_GPCM_TRLX_SET | OR_GPCM_EAD)
|
|
@@ -349,11 +349,11 @@
|
|
|
|
|
|
#define CONFIG_SYS_BR3_PRELIM (\
|
|
|
CONFIG_SYS_PAXE_BASE | \
|
|
|
- (1 << BR_PS_SHIFT) | \
|
|
|
+ BR_PS_8 | \
|
|
|
BR_V)
|
|
|
|
|
|
#define CONFIG_SYS_OR3_PRELIM (\
|
|
|
- MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
|
|
|
+ OR_AM_256MB | \
|
|
|
OR_GPCM_CSNT | \
|
|
|
OR_GPCM_ACS_DIV2 | \
|
|
|
OR_GPCM_SCY_2 | \
|
|
@@ -368,11 +368,11 @@
|
|
|
|
|
|
#define CONFIG_SYS_BR4_PRELIM (\
|
|
|
CONFIG_SYS_BFTIC3_BASE |\
|
|
|
- (1 << BR_PS_SHIFT) | \
|
|
|
+ BR_PS_8 | \
|
|
|
BR_V)
|
|
|
|
|
|
#define CONFIG_SYS_OR4_PRELIM (\
|
|
|
- MEG_TO_AM(CONFIG_SYS_BFTIC3_SIZE) |\
|
|
|
+ OR_AM_256MB|\
|
|
|
OR_GPCM_CSNT | \
|
|
|
OR_GPCM_ACS_DIV2 |\
|
|
|
OR_GPCM_SCY_2 |\
|