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sysreset: Add Octeon sysreset driver

This patch adds a UCLASS_SYSRESET sysreset driver for the Octeon SoC
family.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Stefan Roese 3 years ago
parent
commit
59aea37abf
3 changed files with 60 additions and 0 deletions
  1. 7 0
      drivers/sysreset/Kconfig
  2. 1 0
      drivers/sysreset/Makefile
  3. 52 0
      drivers/sysreset/sysreset_octeon.c

+ 7 - 0
drivers/sysreset/Kconfig

@@ -57,6 +57,13 @@ config SYSRESET_MICROBLAZE
 	help
 	  This is soft reset on Microblaze which does jump to 0x0 address.
 
+config SYSRESET_OCTEON
+	bool "Enable support for Marvell Octeon SoC family"
+	depends on ARCH_OCTEON
+	help
+	  This enables the system reset driver support for Marvell Octeon
+	  SoCs.
+
 config SYSRESET_PSCI
 	bool "Enable support for PSCI System Reset"
 	depends on ARM_PSCI_FW

+ 1 - 0
drivers/sysreset/Makefile

@@ -10,6 +10,7 @@ obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
 obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o
 obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o
 obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
+obj-$(CONFIG_SYSRESET_OCTEON) += sysreset_octeon.o
 obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
 obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
 obj-$(CONFIG_SYSRESET_SOCFPGA_S10) += sysreset_socfpga_s10.o

+ 52 - 0
drivers/sysreset/sysreset_octeon.c

@@ -0,0 +1,52 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Stefan Roese <sr@denx.de>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <sysreset.h>
+#include <asm/io.h>
+
+#define RST_SOFT_RST		0x0080
+
+struct octeon_sysreset_data {
+	void __iomem *base;
+};
+
+static int octeon_sysreset_request(struct udevice *dev, enum sysreset_t type)
+{
+	struct octeon_sysreset_data *data = dev_get_priv(dev);
+
+	writeq(1, data->base + RST_SOFT_RST);
+
+	return -EINPROGRESS;
+}
+
+static int octeon_sysreset_probe(struct udevice *dev)
+{
+	struct octeon_sysreset_data *data = dev_get_priv(dev);
+
+	data->base = dev_remap_addr(dev);
+
+	return 0;
+}
+
+static struct sysreset_ops octeon_sysreset = {
+	.request = octeon_sysreset_request,
+};
+
+static const struct udevice_id octeon_sysreset_ids[] = {
+	{ .compatible = "mrvl,cn7xxx-rst" },
+	{ }
+};
+
+U_BOOT_DRIVER(sysreset_octeon) = {
+	.id	= UCLASS_SYSRESET,
+	.name	= "octeon_sysreset",
+	.priv_auto_alloc_size = sizeof(struct octeon_sysreset_data),
+	.ops	= &octeon_sysreset,
+	.probe	= octeon_sysreset_probe,
+	.of_match = octeon_sysreset_ids,
+};