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@@ -827,53 +827,6 @@ u32 mxc_get_clock(enum mxc_clock clk)
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}
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#if defined(CONFIG_IMX8MP) && defined(CONFIG_DWC_ETH_QOS)
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-int set_clk_eqos(enum enet_freq type)
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-{
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- u32 target;
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- u32 enet1_ref;
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-
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- switch (type) {
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- case ENET_125MHZ:
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- enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK;
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- break;
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- case ENET_50MHZ:
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- enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK;
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- break;
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- case ENET_25MHZ:
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- enet1_ref = ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK;
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- break;
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- default:
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- return -EINVAL;
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- }
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-
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- /* disable the clock first */
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- clock_enable(CCGR_QOS_ETHENET, 0);
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- clock_enable(CCGR_SDMA2, 0);
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-
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- /* set enet axi clock 266Mhz */
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- target = CLK_ROOT_ON | ENET_AXI_CLK_ROOT_FROM_SYS1_PLL_266M |
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- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
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- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
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- clock_set_target_val(ENET_AXI_CLK_ROOT, target);
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-
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- target = CLK_ROOT_ON | enet1_ref |
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- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
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- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV1);
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- clock_set_target_val(ENET_QOS_CLK_ROOT, target);
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-
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- target = CLK_ROOT_ON |
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- ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK |
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- CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV1) |
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- CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV4);
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- clock_set_target_val(ENET_QOS_TIMER_CLK_ROOT, target);
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-
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- /* enable clock */
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- clock_enable(CCGR_QOS_ETHENET, 1);
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- clock_enable(CCGR_SDMA2, 1);
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-
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- return 0;
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-}
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-
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static int imx8mp_eqos_interface_init(struct udevice *dev,
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phy_interface_t interface_type)
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{
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