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@@ -0,0 +1,119 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * MMIO interface for QFW
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+ *
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+ * (C) Copyright 2015 Miao Yan <yanmiaobest@gmail.com>
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+ * (C) Copyright 2021 Asherah Connor <ashe@kivikakk.ee>
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+ */
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+
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+#define LOG_CATEGORY UCLASS_QFW
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+
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+#include <asm/types.h>
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+#include <asm/io.h>
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+#include <dm.h>
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+#include <dm/device.h>
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+#include <qfw.h>
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+
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+struct qfw_mmio {
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+ /*
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+ * Each access to the 64-bit data register can be 8/16/32/64 bits wide.
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+ */
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+ union {
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+ u8 data8;
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+ u16 data16;
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+ u32 data32;
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+ u64 data64;
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+ };
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+ u16 selector;
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+ u8 padding[6];
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+ u64 dma;
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+};
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+
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+struct qfw_mmio_plat {
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+ volatile struct qfw_mmio *mmio;
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+};
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+
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+static void qfw_mmio_read_entry_io(struct udevice *dev, u16 entry, u32 size,
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+ void *address)
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+{
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+ struct qfw_mmio_plat *plat = dev_get_plat(dev);
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+
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+ /*
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+ * writing FW_CFG_INVALID will cause read operation to resume at last
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+ * offset, otherwise read will start at offset 0
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+ *
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+ * Note: on platform where the control register is MMIO, the register
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+ * is big endian.
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+ */
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+ if (entry != FW_CFG_INVALID)
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+ plat->mmio->selector = cpu_to_be16(entry);
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+
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+ /* the endianness of data register is string-preserving */
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+ while (size >= 8) {
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+ *(u64 *)address = plat->mmio->data64;
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+ address += 8;
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+ size -= 8;
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+ }
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+ while (size >= 4) {
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+ *(u32 *)address = plat->mmio->data32;
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+ address += 4;
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+ size -= 4;
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+ }
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+ while (size >= 2) {
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+ *(u16 *)address = plat->mmio->data16;
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+ address += 2;
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+ size -= 2;
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+ }
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+ while (size >= 1) {
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+ *(u8 *)address = plat->mmio->data8;
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+ address += 1;
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+ size -= 1;
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+ }
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+}
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+
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+/* Read configuration item using fw_cfg DMA interface */
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+static void qfw_mmio_read_entry_dma(struct udevice *dev, struct qfw_dma *dma)
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+{
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+ struct qfw_mmio_plat *plat = dev_get_plat(dev);
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+
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+ /* the DMA address register is big-endian */
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+ plat->mmio->dma = cpu_to_be64((uintptr_t)dma);
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+
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+ while (be32_to_cpu(dma->control) & ~FW_CFG_DMA_ERROR);
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+}
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+
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+static int qfw_mmio_of_to_plat(struct udevice *dev)
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+{
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+ struct qfw_mmio_plat *plat = dev_get_plat(dev);
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+
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+ plat->mmio = map_physmem(dev_read_addr(dev),
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+ sizeof(struct qfw_mmio),
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+ MAP_NOCACHE);
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+
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+ return 0;
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+}
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+
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+static int qfw_mmio_probe(struct udevice *dev)
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+{
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+ return qfw_register(dev);
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+}
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+
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+static struct dm_qfw_ops qfw_mmio_ops = {
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+ .read_entry_io = qfw_mmio_read_entry_io,
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+ .read_entry_dma = qfw_mmio_read_entry_dma,
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+};
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+
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+static const struct udevice_id qfw_mmio_ids[] = {
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+ { .compatible = "qemu,fw-cfg-mmio" },
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+ {}
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+};
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+
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+U_BOOT_DRIVER(qfw_mmio) = {
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+ .name = "qfw_mmio",
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+ .id = UCLASS_QFW,
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+ .of_match = qfw_mmio_ids,
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+ .plat_auto = sizeof(struct qfw_mmio_plat),
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+ .of_to_plat = qfw_mmio_of_to_plat,
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+ .probe = qfw_mmio_probe,
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+ .ops = &qfw_mmio_ops,
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+};
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