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@@ -110,7 +110,7 @@
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};
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};
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- cpu0_opp_table: cpu0-opp-table {
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+ cpu0_opp_table: opp-table-0 {
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compatible = "operating-points-v2";
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opp-shared;
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@@ -143,7 +143,7 @@
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};
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arm-pmu {
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- compatible = "arm,cortex-a53-pmu";
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+ compatible = "arm,cortex-a35-pmu";
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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@@ -151,11 +151,6 @@
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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- dmc: dmc {
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- compatible = "rockchip,px30-dmc", "syscon";
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- reg = <0x0 0xff2a0000 0x0 0x1000>;
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- };
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-
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display_subsystem: display-subsystem {
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compatible = "rockchip,display-subsystem";
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ports = <&vopb_out>, <&vopl_out>;
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@@ -249,28 +244,31 @@
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#size-cells = <0>;
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/* These power domains are grouped by VD_LOGIC */
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- pd_usb@PX30_PD_USB {
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+ power-domain@PX30_PD_USB {
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reg = <PX30_PD_USB>;
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clocks = <&cru HCLK_HOST>,
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<&cru HCLK_OTG>,
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<&cru SCLK_OTG_ADP>;
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pm_qos = <&qos_usb_host>, <&qos_usb_otg>;
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+ #power-domain-cells = <0>;
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};
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- pd_sdcard@PX30_PD_SDCARD {
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+ power-domain@PX30_PD_SDCARD {
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reg = <PX30_PD_SDCARD>;
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clocks = <&cru HCLK_SDMMC>,
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<&cru SCLK_SDMMC>;
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pm_qos = <&qos_sdmmc>;
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+ #power-domain-cells = <0>;
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};
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- pd_gmac@PX30_PD_GMAC {
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+ power-domain@PX30_PD_GMAC {
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reg = <PX30_PD_GMAC>;
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clocks = <&cru ACLK_GMAC>,
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<&cru PCLK_GMAC>,
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<&cru SCLK_MAC_REF>,
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<&cru SCLK_GMAC_RX_TX>;
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pm_qos = <&qos_gmac>;
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+ #power-domain-cells = <0>;
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};
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- pd_mmc_nand@PX30_PD_MMC_NAND {
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+ power-domain@PX30_PD_MMC_NAND {
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reg = <PX30_PD_MMC_NAND>;
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clocks = <&cru HCLK_NANDC>,
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<&cru HCLK_EMMC>,
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@@ -282,15 +280,17 @@
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<&cru SCLK_SFC>;
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pm_qos = <&qos_emmc>, <&qos_nand>,
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<&qos_sdio>, <&qos_sfc>;
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+ #power-domain-cells = <0>;
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};
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- pd_vpu@PX30_PD_VPU {
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+ power-domain@PX30_PD_VPU {
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reg = <PX30_PD_VPU>;
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clocks = <&cru ACLK_VPU>,
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<&cru HCLK_VPU>,
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<&cru SCLK_CORE_VPU>;
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pm_qos = <&qos_vpu>, <&qos_vpu_r128>;
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+ #power-domain-cells = <0>;
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};
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- pd_vo@PX30_PD_VO {
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+ power-domain@PX30_PD_VO {
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reg = <PX30_PD_VO>;
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clocks = <&cru ACLK_RGA>,
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<&cru ACLK_VOPB>,
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@@ -305,8 +305,9 @@
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<&cru SCLK_VOPB_PWM>;
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pm_qos = <&qos_rga_rd>, <&qos_rga_wr>,
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<&qos_vop_m0>, <&qos_vop_m1>;
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+ #power-domain-cells = <0>;
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};
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- pd_vi@PX30_PD_VI {
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+ power-domain@PX30_PD_VI {
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reg = <PX30_PD_VI>;
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clocks = <&cru ACLK_CIF>,
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<&cru ACLK_ISP>,
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@@ -316,11 +317,13 @@
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pm_qos = <&qos_isp_128>, <&qos_isp_rd>,
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<&qos_isp_wr>, <&qos_isp_m1>,
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<&qos_vip>;
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+ #power-domain-cells = <0>;
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};
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- pd_gpu@PX30_PD_GPU {
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+ power-domain@PX30_PD_GPU {
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reg = <PX30_PD_GPU>;
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clocks = <&cru SCLK_GPU>;
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pm_qos = <&qos_gpu>;
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+ #power-domain-cells = <0>;
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};
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};
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};
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@@ -605,7 +608,7 @@
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};
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wdt: watchdog@ff1e0000 {
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- compatible = "snps,dw-wdt";
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+ compatible = "rockchip,px30-wdt", "snps,dw-wdt";
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reg = <0x0 0xff1e0000 0x0 0x100>;
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clocks = <&cru PCLK_WDT_NS>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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@@ -708,21 +711,15 @@
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clock-names = "pclk", "timer";
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};
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- amba {
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- compatible = "simple-bus";
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- #address-cells = <2>;
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- #size-cells = <2>;
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- ranges;
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-
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- dmac: dmac@ff240000 {
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- compatible = "arm,pl330", "arm,primecell";
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- reg = <0x0 0xff240000 0x0 0x4000>;
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- interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&cru ACLK_DMAC>;
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- clock-names = "apb_pclk";
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- #dma-cells = <1>;
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- };
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+ dmac: dmac@ff240000 {
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+ compatible = "arm,pl330", "arm,primecell";
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+ reg = <0x0 0xff240000 0x0 0x4000>;
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+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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+ arm,pl330-periph-burst;
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+ clocks = <&cru ACLK_DMAC>;
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+ clock-names = "apb_pclk";
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+ #dma-cells = <1>;
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};
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tsadc: tsadc@ff280000 {
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@@ -738,9 +735,9 @@
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rockchip,grf = <&grf>;
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rockchip,hw-tshut-temp = <120000>;
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pinctrl-names = "init", "default", "sleep";
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- pinctrl-0 = <&tsadc_otp_gpio>;
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+ pinctrl-0 = <&tsadc_otp_pin>;
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pinctrl-1 = <&tsadc_otp_out>;
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- pinctrl-2 = <&tsadc_otp_gpio>;
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+ pinctrl-2 = <&tsadc_otp_pin>;
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#thermal-sensor-cells = <1>;
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status = "disabled";
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};
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@@ -789,6 +786,16 @@
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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+
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+ assigned-clocks = <&cru PLL_NPLL>,
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+ <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
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+ <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
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+ <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
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+
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+ assigned-clock-rates = <1188000000>,
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+ <200000000>, <200000000>,
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+ <150000000>, <150000000>,
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+ <100000000>, <200000000>;
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};
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pmucru: clock-controller@ff2bc000 {
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@@ -799,6 +806,13 @@
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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+
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+ assigned-clocks =
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+ <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>,
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+ <&pmucru SCLK_WIFI_PMU>;
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+ assigned-clock-rates =
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+ <1200000000>, <100000000>,
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+ <26000000>;
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};
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usb2phy_grf: syscon@ff2c0000 {
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@@ -808,7 +822,7 @@
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#address-cells = <1>;
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#size-cells = <1>;
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- u2phy: usb2-phy@100 {
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+ u2phy: usb2phy@100 {
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compatible = "rockchip,px30-usb2phy";
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reg = <0x100 0x20>;
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clocks = <&pmucru SCLK_USBPHY_REF>;
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@@ -850,6 +864,19 @@
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status = "disabled";
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};
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+ csi_dphy: phy@ff2f0000 {
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+ compatible = "rockchip,px30-csi-dphy";
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+ reg = <0x0 0xff2f0000 0x0 0x4000>;
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+ clocks = <&cru PCLK_MIPICSIPHY>;
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+ clock-names = "pclk";
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+ #phy-cells = <0>;
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+ power-domains = <&power PX30_PD_VI>;
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+ resets = <&cru SRST_MIPICSIPHY_P>;
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+ reset-names = "apb";
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+ rockchip,grf = <&grf>;
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+ status = "disabled";
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+ };
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+
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usb20_otg: usb@ff300000 {
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compatible = "rockchip,px30-usb", "rockchip,rk3066-usb",
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"snps,dwc2";
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@@ -861,7 +888,6 @@
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g-np-tx-fifo-size = <16>;
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g-rx-fifo-size = <280>;
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g-tx-fifo-size = <256 128 128 64 32 16>;
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- g-use-dma;
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phys = <&u2phy_otg>;
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phy-names = "usb2-phy";
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power-domains = <&power PX30_PD_USB>;
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@@ -873,7 +899,6 @@
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reg = <0x0 0xff340000 0x0 0x10000>;
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_HOST>;
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- clock-names = "usbhost";
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phys = <&u2phy_host>;
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phy-names = "usb";
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power-domains = <&power PX30_PD_USB>;
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@@ -885,7 +910,6 @@
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reg = <0x0 0xff350000 0x0 0x10000>;
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_HOST>;
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- clock-names = "usbhost";
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phys = <&u2phy_host>;
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phy-names = "usb";
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power-domains = <&power PX30_PD_USB>;
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@@ -915,13 +939,14 @@
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status = "disabled";
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};
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- sdmmc: dwmmc@ff370000 {
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+ sdmmc: mmc@ff370000 {
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compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
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reg = <0x0 0xff370000 0x0 0x4000>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
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<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
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- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
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+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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+ bus-width = <4>;
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fifo-depth = <0x100>;
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max-frequency = <150000000>;
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pinctrl-names = "default";
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@@ -930,13 +955,14 @@
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status = "disabled";
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};
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- sdio: dwmmc@ff380000 {
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+ sdio: mmc@ff380000 {
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compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
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reg = <0x0 0xff380000 0x0 0x4000>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
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<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
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- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
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+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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+ bus-width = <4>;
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fifo-depth = <0x100>;
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max-frequency = <150000000>;
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pinctrl-names = "default";
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@@ -945,13 +971,14 @@
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status = "disabled";
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};
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- emmc: dwmmc@ff390000 {
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+ emmc: mmc@ff390000 {
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compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc";
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reg = <0x0 0xff390000 0x0 0x4000>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
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<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
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- clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
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+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
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+ bus-width = <8>;
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fifo-depth = <0x100>;
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max-frequency = <150000000>;
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pinctrl-names = "default";
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@@ -960,18 +987,54 @@
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status = "disabled";
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};
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- sfc: sfc@ff3a0000 {
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+ sfc: spi@ff3a0000 {
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compatible = "rockchip,sfc";
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reg = <0x0 0xff3a0000 0x0 0x4000>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
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clock-names = "clk_sfc", "hclk_sfc";
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- pinctrl-names = "default";
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pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus4>;
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+ pinctrl-names = "default";
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+ power-domains = <&power PX30_PD_MMC_NAND>;
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+ status = "disabled";
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+ };
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+
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+ nfc: nand-controller@ff3b0000 {
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+ compatible = "rockchip,px30-nfc";
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+ reg = <0x0 0xff3b0000 0x0 0x4000>;
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+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
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+ clock-names = "ahb", "nfc";
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+ assigned-clocks = <&cru SCLK_NANDC>;
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+ assigned-clock-rates = <150000000>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0
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+ &flash_rdn &flash_rdy &flash_wrn &flash_dqs>;
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power-domains = <&power PX30_PD_MMC_NAND>;
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status = "disabled";
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};
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+ gpu_opp_table: opp-table-1 {
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+ compatible = "operating-points-v2";
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+
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+ opp-200000000 {
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+ opp-hz = /bits/ 64 <200000000>;
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+ opp-microvolt = <950000>;
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+ };
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+ opp-300000000 {
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+ opp-hz = /bits/ 64 <300000000>;
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+ opp-microvolt = <975000>;
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+ };
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+ opp-400000000 {
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+ opp-hz = /bits/ 64 <400000000>;
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+ opp-microvolt = <1050000>;
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+ };
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+ opp-480000000 {
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+ opp-hz = /bits/ 64 <480000000>;
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+ opp-microvolt = <1125000>;
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+ };
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+ };
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+
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gpu: gpu@ff400000 {
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compatible = "rockchip,px30-mali", "arm,mali-bifrost";
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reg = <0x0 0xff400000 0x0 0x4000>;
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@@ -982,9 +1045,32 @@
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clocks = <&cru SCLK_GPU>;
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#cooling-cells = <2>;
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power-domains = <&power PX30_PD_GPU>;
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+ operating-points-v2 = <&gpu_opp_table>;
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status = "disabled";
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};
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+ vpu: video-codec@ff442000 {
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+ compatible = "rockchip,px30-vpu";
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+ reg = <0x0 0xff442000 0x0 0x800>;
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+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
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+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "vepu", "vdpu";
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+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
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+ clock-names = "aclk", "hclk";
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+ iommus = <&vpu_mmu>;
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|
+ power-domains = <&power PX30_PD_VPU>;
|
|
|
+ };
|
|
|
+
|
|
|
+ vpu_mmu: iommu@ff442800 {
|
|
|
+ compatible = "rockchip,iommu";
|
|
|
+ reg = <0x0 0xff442800 0x0 0x100>;
|
|
|
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
|
|
|
+ clock-names = "aclk", "iface";
|
|
|
+ #iommu-cells = <0>;
|
|
|
+ power-domains = <&power PX30_PD_VPU>;
|
|
|
+ };
|
|
|
+
|
|
|
dsi: dsi@ff450000 {
|
|
|
compatible = "rockchip,px30-mipi-dsi";
|
|
|
reg = <0x0 0xff450000 0x0 0x10000>;
|
|
@@ -1034,7 +1120,6 @@
|
|
|
reset-names = "axi", "ahb", "dclk";
|
|
|
iommus = <&vopb_mmu>;
|
|
|
power-domains = <&power PX30_PD_VO>;
|
|
|
- rockchip,grf = <&grf>;
|
|
|
status = "disabled";
|
|
|
|
|
|
vopb_out: port {
|
|
@@ -1057,7 +1142,6 @@
|
|
|
compatible = "rockchip,iommu";
|
|
|
reg = <0x0 0xff460f00 0x0 0x100>;
|
|
|
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
- interrupt-names = "vopb_mmu";
|
|
|
clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>;
|
|
|
clock-names = "aclk", "iface";
|
|
|
power-domains = <&power PX30_PD_VO>;
|
|
@@ -1076,7 +1160,6 @@
|
|
|
reset-names = "axi", "ahb", "dclk";
|
|
|
iommus = <&vopl_mmu>;
|
|
|
power-domains = <&power PX30_PD_VO>;
|
|
|
- rockchip,grf = <&grf>;
|
|
|
status = "disabled";
|
|
|
|
|
|
vopl_out: port {
|
|
@@ -1098,8 +1181,7 @@
|
|
|
vopl_mmu: iommu@ff470f00 {
|
|
|
compatible = "rockchip,iommu";
|
|
|
reg = <0x0 0xff470f00 0x0 0x100>;
|
|
|
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
- interrupt-names = "vopl_mmu";
|
|
|
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>;
|
|
|
clock-names = "aclk", "iface";
|
|
|
power-domains = <&power PX30_PD_VO>;
|
|
@@ -1107,103 +1189,144 @@
|
|
|
status = "disabled";
|
|
|
};
|
|
|
|
|
|
+ isp: isp@ff4a0000 {
|
|
|
+ compatible = "rockchip,px30-cif-isp"; /*rk3326-rkisp1*/
|
|
|
+ reg = <0x0 0xff4a0000 0x0 0x8000>;
|
|
|
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
|
|
|
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ interrupt-names = "isp", "mi", "mipi";
|
|
|
+ clocks = <&cru SCLK_ISP>,
|
|
|
+ <&cru ACLK_ISP>,
|
|
|
+ <&cru HCLK_ISP>,
|
|
|
+ <&cru PCLK_ISP>;
|
|
|
+ clock-names = "isp", "aclk", "hclk", "pclk";
|
|
|
+ iommus = <&isp_mmu>;
|
|
|
+ phys = <&csi_dphy>;
|
|
|
+ phy-names = "dphy";
|
|
|
+ power-domains = <&power PX30_PD_VI>;
|
|
|
+ status = "disabled";
|
|
|
+
|
|
|
+ ports {
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+
|
|
|
+ port@0 {
|
|
|
+ reg = <0>;
|
|
|
+ #address-cells = <1>;
|
|
|
+ #size-cells = <0>;
|
|
|
+ };
|
|
|
+ };
|
|
|
+ };
|
|
|
+
|
|
|
+ isp_mmu: iommu@ff4a8000 {
|
|
|
+ compatible = "rockchip,iommu";
|
|
|
+ reg = <0x0 0xff4a8000 0x0 0x100>;
|
|
|
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
+ clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
|
|
|
+ clock-names = "aclk", "iface";
|
|
|
+ power-domains = <&power PX30_PD_VI>;
|
|
|
+ rockchip,disable-mmu-reset;
|
|
|
+ #iommu-cells = <0>;
|
|
|
+ };
|
|
|
+
|
|
|
qos_gmac: qos@ff518000 {
|
|
|
- compatible = "syscon";
|
|
|
+ compatible = "rockchip,px30-qos", "syscon";
|
|
|
reg = <0x0 0xff518000 0x0 0x20>;
|
|
|
};
|
|
|
|
|
|
qos_gpu: qos@ff520000 {
|
|
|
- compatible = "syscon";
|
|
|
+ compatible = "rockchip,px30-qos", "syscon";
|
|
|
reg = <0x0 0xff520000 0x0 0x20>;
|
|
|
};
|
|
|
|
|
|
qos_sdmmc: qos@ff52c000 {
|
|
|
- compatible = "syscon";
|
|
|
+ compatible = "rockchip,px30-qos", "syscon";
|
|
|
reg = <0x0 0xff52c000 0x0 0x20>;
|
|
|
};
|
|
|
|
|
|
qos_emmc: qos@ff538000 {
|
|
|
- compatible = "syscon";
|
|
|
+ compatible = "rockchip,px30-qos", "syscon";
|
|
|
reg = <0x0 0xff538000 0x0 0x20>;
|
|
|
};
|
|
|
|
|
|
qos_nand: qos@ff538080 {
|
|
|
- compatible = "syscon";
|
|
|
+ compatible = "rockchip,px30-qos", "syscon";
|
|
|
reg = <0x0 0xff538080 0x0 0x20>;
|
|
|
};
|
|
|
|
|
|
qos_sdio: qos@ff538100 {
|
|
|
- compatible = "syscon";
|
|
|
+ compatible = "rockchip,px30-qos", "syscon";
|
|
|
reg = <0x0 0xff538100 0x0 0x20>;
|
|
|
};
|
|
|
|
|
|
qos_sfc: qos@ff538180 {
|
|
|
- compatible = "syscon";
|
|
|
+ compatible = "rockchip,px30-qos", "syscon";
|
|
|
reg = <0x0 0xff538180 0x0 0x20>;
|
|
|
};
|
|
|
|
|
|
qos_usb_host: qos@ff540000 {
|
|
|
- compatible = "syscon";
|
|
|
+ compatible = "rockchip,px30-qos", "syscon";
|
|
|
reg = <0x0 0xff540000 0x0 0x20>;
|
|
|
};
|
|
|
|
|
|
qos_usb_otg: qos@ff540080 {
|
|
|
- compatible = "syscon";
|
|
|
+ compatible = "rockchip,px30-qos", "syscon";
|
|
|
reg = <0x0 0xff540080 0x0 0x20>;
|
|
|
};
|
|
|
|
|
|
qos_isp_128: qos@ff548000 {
|
|
|
- compatible = "syscon";
|
|
|
+ compatible = "rockchip,px30-qos", "syscon";
|
|
|
reg = <0x0 0xff548000 0x0 0x20>;
|
|
|
};
|
|
|
|
|
|
qos_isp_rd: qos@ff548080 {
|
|
|
- compatible = "syscon";
|
|
|
+ compatible = "rockchip,px30-qos", "syscon";
|
|
|
reg = <0x0 0xff548080 0x0 0x20>;
|
|
|
};
|
|
|
|
|
|
qos_isp_wr: qos@ff548100 {
|
|
|
- compatible = "syscon";
|
|
|
+ compatible = "rockchip,px30-qos", "syscon";
|
|
|
reg = <0x0 0xff548100 0x0 0x20>;
|
|
|
};
|
|
|
|
|
|
qos_isp_m1: qos@ff548180 {
|
|
|
- compatible = "syscon";
|
|
|
+ compatible = "rockchip,px30-qos", "syscon";
|
|
|
reg = <0x0 0xff548180 0x0 0x20>;
|
|
|
};
|
|
|
|
|
|
qos_vip: qos@ff548200 {
|
|
|
- compatible = "syscon";
|
|
|
+ compatible = "rockchip,px30-qos", "syscon";
|
|
|
reg = <0x0 0xff548200 0x0 0x20>;
|
|
|
};
|
|
|
|
|
|
qos_rga_rd: qos@ff550000 {
|
|
|
- compatible = "syscon";
|
|
|
+ compatible = "rockchip,px30-qos", "syscon";
|
|
|
reg = <0x0 0xff550000 0x0 0x20>;
|
|
|
};
|
|
|
|
|
|
qos_rga_wr: qos@ff550080 {
|
|
|
- compatible = "syscon";
|
|
|
+ compatible = "rockchip,px30-qos", "syscon";
|
|
|
reg = <0x0 0xff550080 0x0 0x20>;
|
|
|
};
|
|
|
|
|
|
qos_vop_m0: qos@ff550100 {
|
|
|
- compatible = "syscon";
|
|
|
+ compatible = "rockchip,px30-qos", "syscon";
|
|
|
reg = <0x0 0xff550100 0x0 0x20>;
|
|
|
};
|
|
|
|
|
|
qos_vop_m1: qos@ff550180 {
|
|
|
- compatible = "syscon";
|
|
|
+ compatible = "rockchip,px30-qos", "syscon";
|
|
|
reg = <0x0 0xff550180 0x0 0x20>;
|
|
|
};
|
|
|
|
|
|
qos_vpu: qos@ff558000 {
|
|
|
- compatible = "syscon";
|
|
|
+ compatible = "rockchip,px30-qos", "syscon";
|
|
|
reg = <0x0 0xff558000 0x0 0x20>;
|
|
|
};
|
|
|
|
|
|
qos_vpu_r128: qos@ff558080 {
|
|
|
- compatible = "syscon";
|
|
|
+ compatible = "rockchip,px30-qos", "syscon";
|
|
|
reg = <0x0 0xff558080 0x0 0x20>;
|
|
|
};
|
|
|
|
|
@@ -1215,7 +1338,7 @@
|
|
|
#size-cells = <2>;
|
|
|
ranges;
|
|
|
|
|
|
- gpio0: gpio0@ff040000 {
|
|
|
+ gpio0: gpio@ff040000 {
|
|
|
compatible = "rockchip,gpio-bank";
|
|
|
reg = <0x0 0xff040000 0x0 0x100>;
|
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
|
@@ -1227,7 +1350,7 @@
|
|
|
#interrupt-cells = <2>;
|
|
|
};
|
|
|
|
|
|
- gpio1: gpio1@ff250000 {
|
|
|
+ gpio1: gpio@ff250000 {
|
|
|
compatible = "rockchip,gpio-bank";
|
|
|
reg = <0x0 0xff250000 0x0 0x100>;
|
|
|
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
@@ -1239,7 +1362,7 @@
|
|
|
#interrupt-cells = <2>;
|
|
|
};
|
|
|
|
|
|
- gpio2: gpio2@ff260000 {
|
|
|
+ gpio2: gpio@ff260000 {
|
|
|
compatible = "rockchip,gpio-bank";
|
|
|
reg = <0x0 0xff260000 0x0 0x100>;
|
|
|
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
@@ -1251,7 +1374,7 @@
|
|
|
#interrupt-cells = <2>;
|
|
|
};
|
|
|
|
|
|
- gpio3: gpio3@ff270000 {
|
|
|
+ gpio3: gpio@ff270000 {
|
|
|
compatible = "rockchip,gpio-bank";
|
|
|
reg = <0x0 0xff270000 0x0 0x100>;
|
|
|
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
@@ -1375,7 +1498,7 @@
|
|
|
};
|
|
|
|
|
|
tsadc {
|
|
|
- tsadc_otp_gpio: tsadc-otp-gpio {
|
|
|
+ tsadc_otp_pin: tsadc-otp-pin {
|
|
|
rockchip,pins =
|
|
|
<0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
|
};
|
|
@@ -1938,7 +2061,7 @@
|
|
|
};
|
|
|
};
|
|
|
|
|
|
- serial_flash {
|
|
|
+ sfc {
|
|
|
sfc_bus4: sfc-bus4 {
|
|
|
rockchip,pins =
|
|
|
<1 RK_PA0 3 &pcfg_pull_none>,
|