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+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
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+/*
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+ * Copyright (C) 2022 Starfive, Inc.
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+ * Author: samin <samin.guo@starfivetech.com>
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+ * yanhong <yanhong.wang@starfivetech.com>
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+ */
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+
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+#ifndef __DT_BINDINGS_RESET_STARFIVE_JH7110_H__
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+#define __DT_BINDINGS_RESET_STARFIVE_JH7110_H__
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+
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+/*
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+ * group[0]: syscrg: assert0
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+ */
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+#define RSTN_U0_JTAG2APB_PRESETN 0
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+#define RSTN_U0_SYS_SYSCON_PRESETN 1
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+#define RSTN_U0_SYS_IOMUX_PRESETN 2
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+#define RSTN_U0_U7MC_RST_BUS 3
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+#define RSTN_U0_U7MC_DEBUG 4
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+#define RSTN_U0_U7MC_CORE0 5
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+#define RSTN_U0_U7MC_CORE1 6
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+#define RSTN_U0_U7MC_CORE2 7
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+#define RSTN_U0_U7MC_CORE3 8
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+#define RSTN_U0_U7MC_CORE4 9
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+#define RSTN_U0_U7MC_CORE0_ST 10
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+#define RSTN_U0_U7MC_CORE1_ST 11
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+#define RSTN_U0_U7MC_CORE2_ST 12
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+#define RSTN_U0_U7MC_CORE3_ST 13
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+#define RSTN_U0_U7MC_CORE4_ST 14
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+#define RSTN_U0_U7MC_TRACE_RST0 15
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+#define RSTN_U0_U7MC_TRACE_RST1 16
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+#define RSTN_U0_U7MC_TRACE_RST2 17
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+#define RSTN_U0_U7MC_TRACE_RST3 18
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+#define RSTN_U0_U7MC_TRACE_RST4 19
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+#define RSTN_U0_U7MC_TRACE_COM 20
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+#define RSTN_U0_IMG_GPU_APB 21
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+#define RSTN_U0_IMG_GPU_DOMA 22
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+#define RSTN_U0_NOC_BUS_APB_BUS_N 23
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+#define RSTN_U0_NOC_BUS_AXICFG0_AXI_N 24
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+#define RSTN_U0_NOC_BUS_CPU_AXI_N 25
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+#define RSTN_U0_NOC_BUS_DISP_AXI_N 26
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+#define RSTN_U0_NOC_BUS_GPU_AXI_N 27
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+#define RSTN_U0_NOC_BUS_ISP_AXI_N 28
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+#define RSTN_U0_NOC_BUS_DDRC_N 29
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+#define RSTN_U0_NOC_BUS_STG_AXI_N 30
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+#define RSTN_U0_NOC_BUS_VDEC_AXI_N 31
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+/*
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+ * group[1]: syscrg: assert1
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+ */
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+#define RSTN_U0_NOC_BUS_VENC_AXI_N 32
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+#define RSTN_U0_AXI_CFG1_DEC_AHB 33
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+#define RSTN_U0_AXI_CFG1_DEC_MAIN 34
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+#define RSTN_U0_AXI_CFG0_DEC_MAIN 35
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+#define RSTN_U0_AXI_CFG0_DEC_MAIN_DIV 36
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+#define RSTN_U0_AXI_CFG0_DEC_HIFI4 37
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+#define RSTN_U0_DDR_AXI 38
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+#define RSTN_U0_DDR_OSC 39
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+#define RSTN_U0_DDR_APB 40
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+#define RSTN_U0_DOM_ISP_TOP_N 41
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+#define RSTN_U0_DOM_ISP_TOP_AXI 42
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+#define RSTN_U0_DOM_VOUT_TOP_SRC 43
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+#define RSTN_U0_CODAJ12_AXI 44
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+#define RSTN_U0_CODAJ12_CORE 45
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+#define RSTN_U0_CODAJ12_APB 46
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+#define RSTN_U0_WAVE511_AXI 47
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+#define RSTN_U0_WAVE511_BPU 48
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+#define RSTN_U0_WAVE511_VCE 49
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+#define RSTN_U0_WAVE511_APB 50
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+#define RSTN_U0_VDEC_JPG_ARB_JPG 51
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+#define RSTN_U0_VDEC_JPG_ARB_MAIN 52
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+#define RSTN_U0_AXIMEM_128B_AXI 53
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+#define RSTN_U0_WAVE420L_AXI 54
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+#define RSTN_U0_WAVE420L_BPU 55
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+#define RSTN_U0_WAVE420L_VCE 56
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+#define RSTN_U0_WAVE420L_APB 57
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+#define RSTN_U1_AXIMEM_128B_AXI 58
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+#define RSTN_U2_AXIMEM_128B_AXI 59
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+#define RSTN_U0_INTMEM_ROM_SRAM_ROM 60
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+#define RSTN_U0_CDNS_QSPI_AHB 61
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+#define RSTN_U0_CDNS_QSPI_APB 62
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+#define RSTN_U0_CDNS_QSPI_REF 63
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+/*
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+ * group[2]: syscrg: assert2
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+ */
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+#define RSTN_U0_DW_SDIO_AHB 64
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+#define RSTN_U1_DW_SDIO_AHB 65
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+#define RSTN_U1_DW_GMAC5_AXI64_A_I 66
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+#define RSTN_U1_DW_GMAC5_AXI64_H_N 67
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+#define RSTN_U0_MAILBOX_RRESETN 68
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+#define RSTN_U0_SSP_SPI_APB 69
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+#define RSTN_U1_SSP_SPI_APB 70
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+#define RSTN_U2_SSP_SPI_APB 71
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+#define RSTN_U3_SSP_SPI_APB 72
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+#define RSTN_U4_SSP_SPI_APB 73
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+#define RSTN_U5_SSP_SPI_APB 74
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+#define RSTN_U6_SSP_SPI_APB 75
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+#define RSTN_U0_DW_I2C_APB 76
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+#define RSTN_U1_DW_I2C_APB 77
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+#define RSTN_U2_DW_I2C_APB 78
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+#define RSTN_U3_DW_I2C_APB 79
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+#define RSTN_U4_DW_I2C_APB 80
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+#define RSTN_U5_DW_I2C_APB 81
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+#define RSTN_U6_DW_I2C_APB 82
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+#define RSTN_U0_DW_UART_APB 83
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+#define RSTN_U0_DW_UART_CORE 84
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+#define RSTN_U1_DW_UART_APB 85
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+#define RSTN_U1_DW_UART_CORE 86
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+#define RSTN_U2_DW_UART_APB 87
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+#define RSTN_U2_DW_UART_CORE 88
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+#define RSTN_U3_DW_UART_APB 89
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+#define RSTN_U3_DW_UART_CORE 90
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+#define RSTN_U4_DW_UART_APB 91
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+#define RSTN_U4_DW_UART_CORE 92
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+#define RSTN_U5_DW_UART_APB 93
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+#define RSTN_U5_DW_UART_CORE 94
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+#define RSTN_U0_CDNS_SPDIF_APB 95
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+/*
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+ * group[3]: syscrg: assert3
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+ */
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+#define RSTN_U0_PWMDAC_APB 96
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+#define RSTN_U0_PDM_4MIC_DMIC 97
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+#define RSTN_U0_PDM_4MIC_APB 98
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+#define RSTN_U0_I2SRX_3CH_APB 99
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+#define RSTN_U0_I2SRX_3CH_BCLK 100
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+#define RSTN_U0_I2STX_4CH_APB 101
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+#define RSTN_U0_I2STX_4CH_BCLK 102
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+#define RSTN_U1_I2STX_4CH_APB 103
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+#define RSTN_U1_I2STX_4CH_BCLK 104
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+#define RSTN_U0_TDM16SLOT_AHB 105
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+#define RSTN_U0_TDM16SLOT_TDM 106
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+#define RSTN_U0_TDM16SLOT_APB 107
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+#define RSTN_U0_PWM_8CH_APB 108
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+#define RSTN_U0_DSKIT_WDT_APB 109
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+#define RSTN_U0_DSKIT_WDT_CORE 110
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+#define RSTN_U0_CAN_CTRL_APB 111
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+#define RSTN_U0_CAN_CTRL_CORE 112
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+#define RSTN_U0_CAN_CTRL_TIMER 113
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+#define RSTN_U1_CAN_CTRL_APB 114
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+#define RSTN_U1_CAN_CTRL_CORE 115
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+#define RSTN_U1_CAN_CTRL_TIMER 116
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+#define RSTN_U0_SI5_TIMER_APB 117
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+#define RSTN_U0_SI5_TIMER_TIMER0 118
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+#define RSTN_U0_SI5_TIMER_TIMER1 119
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+#define RSTN_U0_SI5_TIMER_TIMER2 120
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+#define RSTN_U0_SI5_TIMER_TIMER3 121
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+#define RSTN_U0_INT_CTRL_APB 122
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+#define RSTN_U0_TEMP_SENSOR_APB 123
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+#define RSTN_U0_TEMP_SENSOR_TEMP 124
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+#define RSTN_U0_JTAG_CERTIFICATION_N 125
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+/*
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+ * group[4]: stgcrg
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+ */
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+#define RSTN_U0_STG_SYSCON_PRESETN 128
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+#define RSTN_U0_HIFI4_CORE 129
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+#define RSTN_U0_HIFI4_AXI 130
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+#define RSTN_U0_SEC_TOP_HRESETN 131
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+#define RSTN_U0_E24_CORE 132
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+#define RSTN_U0_DW_DMA1P_AXI 133
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+#define RSTN_U0_DW_DMA1P_AHB 134
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+#define RSTN_U0_CDN_USB_AXI 135
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+#define RSTN_U0_CDN_USB_APB 136
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+#define RSTN_U0_CDN_USB_UTMI_APB 137
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+#define RSTN_U0_CDN_USB_PWRUP 138
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+#define RSTN_U0_PLDA_PCIE_AXI_MST0 139
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+#define RSTN_U0_PLDA_PCIE_AXI_SLV0 140
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+#define RSTN_U0_PLDA_PCIE_AXI_SLV 141
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+#define RSTN_U0_PLDA_PCIE_BRG 142
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+#define RSTN_U0_PLDA_PCIE_CORE 143
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+#define RSTN_U0_PLDA_PCIE_APB 144
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+#define RSTN_U1_PLDA_PCIE_AXI_MST0 145
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+#define RSTN_U1_PLDA_PCIE_AXI_SLV0 146
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+#define RSTN_U1_PLDA_PCIE_AXI_SLV 147
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+#define RSTN_U1_PLDA_PCIE_BRG 148
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+#define RSTN_U1_PLDA_PCIE_CORE 149
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+#define RSTN_U1_PLDA_PCIE_APB 150
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+/*
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+ * group[5]: aoncrg
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+ */
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+#define RSTN_U0_DW_GMAC5_AXI64_AXI 160
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+#define RSTN_U0_DW_GMAC5_AXI64_AHB 161
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+#define RSTN_U0_AON_IOMUX_PRESETN 162
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+#define RSTN_U0_PMU_APB 163
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+#define RSTN_U0_PMU_WKUP 164
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+#define RSTN_U0_RTC_HMS_APB 165
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+#define RSTN_U0_RTC_HMS_CAL 166
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+#define RSTN_U0_RTC_HMS_OSC32K 167
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+/*
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+ * group[6]: ispcrg
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+ */
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+#define RSTN_U0_ISPV2_TOP_WRAPPER_P 192
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+#define RSTN_U0_ISPV2_TOP_WRAPPER_C 193
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+#define RSTN_U0_M31DPHY_HW 194
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+#define RSTN_U0_M31DPHY_B09_ALWAYS_ON 195
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+#define RSTN_U0_VIN_N_PCLK 196
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+#define RSTN_U0_VIN_N_PIXEL_CLK_IF0 197
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+#define RSTN_U0_VIN_N_PIXEL_CLK_IF1 198
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+#define RSTN_U0_VIN_N_PIXEL_CLK_IF2 199
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+#define RSTN_U0_VIN_N_PIXEL_CLK_IF3 200
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+#define RSTN_U0_VIN_N_SYS_CLK 201
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+#define RSTN_U0_VIN_P_AXIRD 202
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+#define RSTN_U0_VIN_P_AXIWR 203
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+/*
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+ * group[7]: voutcrg
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+ */
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+#define RSTN_U0_DC8200_AXI 224
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+#define RSTN_U0_DC8200_AHB 225
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+#define RSTN_U0_DC8200_CORE 226
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+#define RSTN_U0_CDNS_DSITX_DPI 227
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+#define RSTN_U0_CDNS_DSITX_APB 228
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+#define RSTN_U0_CDNS_DSITX_RXESC 229
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+#define RSTN_U0_CDNS_DSITX_SYS 230
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+#define RSTN_U0_CDNS_DSITX_TXBYTEHS 231
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+#define RSTN_U0_CDNS_DSITX_TXESC 232
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+#define RSTN_U0_HDMI_TX_HDMI 233
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+#define RSTN_U0_MIPITX_DPHY_SYS 234
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+#define RSTN_U0_MIPITX_DPHY_TXBYTEHS 235
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+
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+#define RSTN_JH7110_RESET_END 236
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+
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+#endif /* __DT_BINDINGS_RESET_STARFIVE_JH7110_H__ */
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