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@@ -623,19 +623,6 @@
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status = "disabled";
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};
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- i2c6: i2c@12060000 {
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- compatible = "snps,designware-i2c";
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- reg = <0x0 0x12060000 0x0 0x10000>;
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- clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
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- <&clkgen JH7110_I2C6_CLK_APB>;
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- clock-names = "ref", "pclk";
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- resets = <&rstgen RSTN_U6_DW_I2C_APB>;
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- interrupts = <51>;
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- #address-cells = <1>;
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- #size-cells = <0>;
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- status = "disabled";
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- };
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-
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i2c0: i2c@10030000 {
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compatible = "snps,designware-i2c";
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reg = <0x0 0x10030000 0x0 0x10000>;
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@@ -675,6 +662,32 @@
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status = "disabled";
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};
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+ i2c3: i2c@12030000 {
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+ compatible = "snps,designware-i2c";
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+ reg = <0x0 0x12030000 0x0 0x10000>;
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+ clocks = <&clkgen JH7110_I2C3_CLK_CORE>,
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+ <&clkgen JH7110_I2C3_CLK_APB>;
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+ clock-names = "ref", "pclk";
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+ resets = <&rstgen RSTN_U3_DW_I2C_APB>;
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+ interrupts = <48>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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+ i2c4: i2c@12040000 {
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+ compatible = "snps,designware-i2c";
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+ reg = <0x0 0x12040000 0x0 0x10000>;
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+ clocks = <&clkgen JH7110_I2C4_CLK_CORE>,
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+ <&clkgen JH7110_I2C4_CLK_APB>;
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+ clock-names = "ref", "pclk";
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+ resets = <&rstgen RSTN_U4_DW_I2C_APB>;
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+ interrupts = <49>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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i2c5: i2c@12050000 {
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compatible = "snps,designware-i2c";
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reg = <0x0 0x12050000 0x0 0x10000>;
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@@ -688,6 +701,19 @@
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status = "disabled";
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};
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+ i2c6: i2c@12060000 {
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+ compatible = "snps,designware-i2c";
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+ reg = <0x0 0x12060000 0x0 0x10000>;
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+ clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
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+ <&clkgen JH7110_I2C6_CLK_APB>;
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+ clock-names = "ref", "pclk";
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+ resets = <&rstgen RSTN_U6_DW_I2C_APB>;
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+ interrupts = <51>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ status = "disabled";
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+ };
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+
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/* unremovable emmc as mmcblk0 */
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sdio0: sdio0@16010000 {
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compatible = "snps,dw-mshc";
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