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@@ -161,97 +161,6 @@ static struct pci_device_id supported[] = {
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{}
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};
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-
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-int pcnet_initialize(bd_t *bis)
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-{
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- pci_dev_t devbusfn;
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- struct eth_device *dev;
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- u16 command, status;
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- int dev_nr = 0;
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- u32 bar;
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-
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- PCNET_DEBUG1("\npcnet_initialize...\n");
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-
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- for (dev_nr = 0;; dev_nr++) {
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-
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- /*
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- * Find the PCnet PCI device(s).
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- */
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- devbusfn = pci_find_devices(supported, dev_nr);
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- if (devbusfn < 0)
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- break;
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-
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- /*
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- * Allocate and pre-fill the device structure.
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- */
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- dev = calloc(1, sizeof(*dev));
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- if (!dev) {
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- printf("pcnet: Can not allocate memory\n");
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- break;
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- }
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-
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- /*
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- * We only maintain one structure because the drivers will
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- * never be used concurrently. In 32bit mode the RX and TX
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- * ring entries must be aligned on 16-byte boundaries.
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- */
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- if (!lp) {
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- lp = malloc_cache_aligned(sizeof(*lp));
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- lp->uc = map_physmem((phys_addr_t)&lp->ucp,
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- sizeof(lp->ucp), MAP_NOCACHE);
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- flush_dcache_range((unsigned long)lp,
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- (unsigned long)lp + sizeof(*lp));
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- }
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-
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- dev->priv = (void *)(unsigned long)devbusfn;
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- sprintf(dev->name, "pcnet#%d", dev_nr);
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-
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- /*
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- * Setup the PCI device.
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- */
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- pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &bar);
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- dev->iobase = pci_mem_to_phys(devbusfn, bar);
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- dev->iobase &= ~0xf;
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-
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- PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ",
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- dev->name, devbusfn, (unsigned long)dev->iobase);
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-
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- command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
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- pci_write_config_word(devbusfn, PCI_COMMAND, command);
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- pci_read_config_word(devbusfn, PCI_COMMAND, &status);
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- if ((status & command) != command) {
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- printf("%s: Couldn't enable IO access or Bus Mastering\n",
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- dev->name);
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- free(dev);
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- continue;
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- }
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-
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- pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
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-
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- /*
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- * Probe the PCnet chip.
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- */
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- if (pcnet_probe(dev, bis, dev_nr) < 0) {
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- free(dev);
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- continue;
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- }
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-
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- /*
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- * Setup device structure and register the driver.
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- */
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- dev->init = pcnet_init;
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- dev->halt = pcnet_halt;
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- dev->send = pcnet_send;
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- dev->recv = pcnet_recv;
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-
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- eth_register(dev);
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- }
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-
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- udelay(10 * 1000);
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-
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- return dev_nr;
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-}
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-
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static int pcnet_probe(struct eth_device *dev, bd_t *bis, int dev_nr)
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{
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int chip_version;
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@@ -548,3 +457,92 @@ static void pcnet_halt(struct eth_device *dev)
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if (i <= 0)
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printf("%s: TIMEOUT: controller reset failed\n", dev->name);
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}
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+
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+int pcnet_initialize(bd_t *bis)
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+{
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+ pci_dev_t devbusfn;
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+ struct eth_device *dev;
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+ u16 command, status;
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+ int dev_nr = 0;
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+ u32 bar;
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+
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+ PCNET_DEBUG1("\npcnet_initialize...\n");
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+
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+ for (dev_nr = 0; ; dev_nr++) {
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+ /*
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+ * Find the PCnet PCI device(s).
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+ */
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+ devbusfn = pci_find_devices(supported, dev_nr);
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+ if (devbusfn < 0)
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+ break;
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+
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+ /*
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+ * Allocate and pre-fill the device structure.
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+ */
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+ dev = calloc(1, sizeof(*dev));
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+ if (!dev) {
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+ printf("pcnet: Can not allocate memory\n");
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+ break;
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+ }
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+
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+ /*
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+ * We only maintain one structure because the drivers will
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+ * never be used concurrently. In 32bit mode the RX and TX
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+ * ring entries must be aligned on 16-byte boundaries.
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+ */
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+ if (!lp) {
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+ lp = malloc_cache_aligned(sizeof(*lp));
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+ lp->uc = map_physmem((phys_addr_t)&lp->ucp,
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+ sizeof(lp->ucp), MAP_NOCACHE);
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+ flush_dcache_range((unsigned long)lp,
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+ (unsigned long)lp + sizeof(*lp));
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+ }
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+
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+ dev->priv = (void *)(unsigned long)devbusfn;
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+ sprintf(dev->name, "pcnet#%d", dev_nr);
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+
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+ /*
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+ * Setup the PCI device.
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+ */
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+ pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &bar);
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+ dev->iobase = pci_mem_to_phys(devbusfn, bar);
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+ dev->iobase &= ~0xf;
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+
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+ PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%lx: ",
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+ dev->name, devbusfn, (unsigned long)dev->iobase);
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+
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+ command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
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+ pci_write_config_word(devbusfn, PCI_COMMAND, command);
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+ pci_read_config_word(devbusfn, PCI_COMMAND, &status);
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+ if ((status & command) != command) {
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+ printf("%s: Couldn't enable IO access or Bus Mastering\n",
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+ dev->name);
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+ free(dev);
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+ continue;
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+ }
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+
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+ pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
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+
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+ /*
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+ * Probe the PCnet chip.
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+ */
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+ if (pcnet_probe(dev, bis, dev_nr) < 0) {
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+ free(dev);
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+ continue;
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+ }
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+
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+ /*
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+ * Setup device structure and register the driver.
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+ */
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+ dev->init = pcnet_init;
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+ dev->halt = pcnet_halt;
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+ dev->send = pcnet_send;
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+ dev->recv = pcnet_recv;
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+
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+ eth_register(dev);
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+ }
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+
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+ udelay(10 * 1000);
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+
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+ return dev_nr;
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+}
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