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@@ -28,6 +28,7 @@
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#include <common.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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+#include <wait_bit.h>
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#include "cadence_qspi.h"
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#define CQSPI_REG_POLL_US (1) /* 1us */
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@@ -192,128 +193,6 @@ static unsigned int cadence_qspi_apb_cmd2addr(const unsigned char *addr_buf,
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return addr;
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}
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-static void cadence_qspi_apb_read_fifo_data(void *dest,
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- const void *src_ahb_addr, unsigned int bytes)
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-{
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- unsigned int temp;
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- int remaining = bytes;
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- unsigned int *dest_ptr = (unsigned int *)dest;
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- unsigned int *src_ptr = (unsigned int *)src_ahb_addr;
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-
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- while (remaining >= sizeof(dest_ptr)) {
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- *dest_ptr = readl(src_ptr);
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- remaining -= sizeof(src_ptr);
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- dest_ptr++;
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- }
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- if (remaining) {
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- /* dangling bytes */
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- temp = readl(src_ptr);
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- memcpy(dest_ptr, &temp, remaining);
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- }
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-
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- return;
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-}
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-
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-static void cadence_qspi_apb_write_fifo_data(const void *dest_ahb_addr,
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- const void *src, unsigned int bytes)
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-{
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- unsigned int temp = 0;
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- int i;
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- int remaining = bytes;
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- unsigned int *dest_ptr = (unsigned int *)dest_ahb_addr;
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- unsigned int *src_ptr = (unsigned int *)src;
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-
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- while (remaining >= CQSPI_FIFO_WIDTH) {
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- for (i = CQSPI_FIFO_WIDTH/sizeof(src_ptr) - 1; i >= 0; i--)
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- writel(*(src_ptr+i), dest_ptr+i);
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- src_ptr += CQSPI_FIFO_WIDTH/sizeof(src_ptr);
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- remaining -= CQSPI_FIFO_WIDTH;
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- }
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- if (remaining) {
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- /* dangling bytes */
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- i = remaining/sizeof(dest_ptr);
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- memcpy(&temp, src_ptr+i, remaining % sizeof(dest_ptr));
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- writel(temp, dest_ptr+i);
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- for (--i; i >= 0; i--)
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- writel(*(src_ptr+i), dest_ptr+i);
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- }
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- return;
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-}
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-
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-/* Read from SRAM FIFO with polling SRAM fill level. */
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-static int qspi_read_sram_fifo_poll(const void *reg_base, void *dest_addr,
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- const void *src_addr, unsigned int num_bytes)
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-{
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- unsigned int remaining = num_bytes;
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- unsigned int retry;
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- unsigned int sram_level = 0;
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- unsigned char *dest = (unsigned char *)dest_addr;
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-
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- while (remaining > 0) {
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- retry = CQSPI_REG_RETRY;
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- while (retry--) {
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- sram_level = CQSPI_GET_RD_SRAM_LEVEL(reg_base);
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- if (sram_level)
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- break;
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- udelay(1);
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- }
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-
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- if (!retry) {
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- printf("QSPI: No receive data after polling for %d times\n",
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- CQSPI_REG_RETRY);
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- return -1;
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- }
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-
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- sram_level *= CQSPI_FIFO_WIDTH;
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- sram_level = sram_level > remaining ? remaining : sram_level;
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-
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- /* Read data from FIFO. */
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- cadence_qspi_apb_read_fifo_data(dest, src_addr, sram_level);
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- dest += sram_level;
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- remaining -= sram_level;
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- udelay(1);
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- }
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- return 0;
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-}
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-
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-/* Write to SRAM FIFO with polling SRAM fill level. */
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-static int qpsi_write_sram_fifo_push(struct cadence_spi_platdata *plat,
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- const void *src_addr, unsigned int num_bytes)
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-{
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- const void *reg_base = plat->regbase;
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- void *dest_addr = plat->ahbbase;
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- unsigned int retry = CQSPI_REG_RETRY;
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- unsigned int sram_level;
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- unsigned int wr_bytes;
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- unsigned char *src = (unsigned char *)src_addr;
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- int remaining = num_bytes;
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- unsigned int page_size = plat->page_size;
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- unsigned int sram_threshold_words = CQSPI_REG_SRAM_THRESHOLD_WORDS;
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-
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- while (remaining > 0) {
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- retry = CQSPI_REG_RETRY;
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- while (retry--) {
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- sram_level = CQSPI_GET_WR_SRAM_LEVEL(reg_base);
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- if (sram_level <= sram_threshold_words)
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- break;
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- }
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- if (!retry) {
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- printf("QSPI: SRAM fill level (0x%08x) not hit lower expected level (0x%08x)",
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- sram_level, sram_threshold_words);
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- return -1;
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- }
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- /* Write a page or remaining bytes. */
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- wr_bytes = (remaining > page_size) ?
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- page_size : remaining;
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-
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- cadence_qspi_apb_write_fifo_data(dest_addr, src, wr_bytes);
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- src += wr_bytes;
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- remaining -= wr_bytes;
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- }
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-
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- return 0;
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-}
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-
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void cadence_qspi_apb_controller_enable(void *reg_base)
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{
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unsigned int reg;
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@@ -742,40 +621,84 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
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return 0;
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}
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+static u32 cadence_qspi_get_rd_sram_level(struct cadence_spi_platdata *plat)
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+{
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+ u32 reg = readl(plat->regbase + CQSPI_REG_SDRAMLEVEL);
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+ reg >>= CQSPI_REG_SDRAMLEVEL_RD_LSB;
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+ return reg & CQSPI_REG_SDRAMLEVEL_RD_MASK;
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+}
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+
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+static int cadence_qspi_wait_for_data(struct cadence_spi_platdata *plat)
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+{
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+ unsigned int timeout = 10000;
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+ u32 reg;
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+
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+ while (timeout--) {
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+ reg = cadence_qspi_get_rd_sram_level(plat);
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+ if (reg)
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+ return reg;
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+ udelay(1);
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+ }
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+
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+ return -ETIMEDOUT;
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+}
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+
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int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
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- unsigned int rxlen, u8 *rxbuf)
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+ unsigned int n_rx, u8 *rxbuf)
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{
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- unsigned int reg;
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+ unsigned int remaining = n_rx;
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+ unsigned int bytes_to_read = 0;
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+ int ret;
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- writel(rxlen, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
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+ writel(n_rx, plat->regbase + CQSPI_REG_INDIRECTRDBYTES);
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/* Start the indirect read transfer */
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writel(CQSPI_REG_INDIRECTRD_START_MASK,
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plat->regbase + CQSPI_REG_INDIRECTRD);
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- if (qspi_read_sram_fifo_poll(plat->regbase, (void *)rxbuf,
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- (const void *)plat->ahbbase, rxlen))
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- goto failrd;
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+ while (remaining > 0) {
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+ ret = cadence_qspi_wait_for_data(plat);
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+ if (ret < 0) {
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+ printf("Indirect write timed out (%i)\n", ret);
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+ goto failrd;
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+ }
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- /* Check flash indirect controller */
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- reg = readl(plat->regbase + CQSPI_REG_INDIRECTRD);
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- if (!(reg & CQSPI_REG_INDIRECTRD_DONE_MASK)) {
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- reg = readl(plat->regbase + CQSPI_REG_INDIRECTRD);
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- printf("QSPI: indirect completion status error with reg 0x%08x\n",
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- reg);
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+ bytes_to_read = ret;
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+
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+ while (bytes_to_read != 0) {
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+ bytes_to_read *= CQSPI_FIFO_WIDTH;
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+ bytes_to_read = bytes_to_read > remaining ?
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+ remaining : bytes_to_read;
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+ /* Handle non-4-byte aligned access to avoid data abort. */
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+ if (((uintptr_t)rxbuf % 4) || (bytes_to_read % 4))
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+ readsb(plat->ahbbase, rxbuf, bytes_to_read);
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+ else
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+ readsl(plat->ahbbase, rxbuf, bytes_to_read >> 2);
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+ rxbuf += bytes_to_read;
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+ remaining -= bytes_to_read;
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+ bytes_to_read = cadence_qspi_get_rd_sram_level(plat);
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+ }
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+ }
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+
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+ /* Check indirect done status */
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+ ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTRD,
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+ CQSPI_REG_INDIRECTRD_DONE_MASK, 1, 10, 0);
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+ if (ret) {
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+ printf("Indirect read completion error (%i)\n", ret);
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goto failrd;
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}
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/* Clear indirect completion status */
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writel(CQSPI_REG_INDIRECTRD_DONE_MASK,
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plat->regbase + CQSPI_REG_INDIRECTRD);
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+
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return 0;
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failrd:
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/* Cancel the indirect read */
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writel(CQSPI_REG_INDIRECTRD_CANCEL_MASK,
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plat->regbase + CQSPI_REG_INDIRECTRD);
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- return -1;
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+ return ret;
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}
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/* Opcode + Address (3/4 bytes) */
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@@ -810,48 +733,45 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
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}
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int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
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- unsigned int txlen, const u8 *txbuf)
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+ unsigned int n_tx, const u8 *txbuf)
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{
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- unsigned int reg = 0;
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- unsigned int retry;
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+ unsigned int page_size = plat->page_size;
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+ unsigned int remaining = n_tx;
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+ unsigned int write_bytes;
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+ int ret;
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/* Configure the indirect read transfer bytes */
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- writel(txlen, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
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+ writel(n_tx, plat->regbase + CQSPI_REG_INDIRECTWRBYTES);
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/* Start the indirect write transfer */
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writel(CQSPI_REG_INDIRECTWR_START_MASK,
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plat->regbase + CQSPI_REG_INDIRECTWR);
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- if (qpsi_write_sram_fifo_push(plat, (const void *)txbuf, txlen))
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- goto failwr;
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-
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- /* Wait until last write is completed (FIFO empty) */
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- retry = CQSPI_REG_RETRY;
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- while (retry--) {
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- reg = CQSPI_GET_WR_SRAM_LEVEL(plat->regbase);
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- if (reg == 0)
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- break;
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-
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- udelay(1);
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- }
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-
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- if (reg != 0) {
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- printf("QSPI: timeout for indirect write\n");
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- goto failwr;
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- }
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+ while (remaining > 0) {
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+ write_bytes = remaining > page_size ? page_size : remaining;
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+ /* Handle non-4-byte aligned access to avoid data abort. */
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+ if (((uintptr_t)txbuf % 4) || (write_bytes % 4))
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+ writesb(plat->ahbbase, txbuf, write_bytes);
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+ else
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+ writesl(plat->ahbbase, txbuf, write_bytes >> 2);
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+
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+ ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_SDRAMLEVEL,
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+ CQSPI_REG_SDRAMLEVEL_WR_MASK <<
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+ CQSPI_REG_SDRAMLEVEL_WR_LSB, 0, 10, 0);
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+ if (ret) {
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+ printf("Indirect write timed out (%i)\n", ret);
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+ goto failwr;
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+ }
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- /* Check flash indirect controller status */
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- retry = CQSPI_REG_RETRY;
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- while (retry--) {
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- reg = readl(plat->regbase + CQSPI_REG_INDIRECTWR);
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- if (reg & CQSPI_REG_INDIRECTWR_DONE_MASK)
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- break;
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- udelay(1);
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+ txbuf += write_bytes;
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+ remaining -= write_bytes;
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}
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- if (!(reg & CQSPI_REG_INDIRECTWR_DONE_MASK)) {
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- printf("QSPI: indirect completion status error with reg 0x%08x\n",
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- reg);
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+ /* Check indirect done status */
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+ ret = wait_for_bit("QSPI", plat->regbase + CQSPI_REG_INDIRECTWR,
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+ CQSPI_REG_INDIRECTWR_DONE_MASK, 1, 10, 0);
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+ if (ret) {
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+ printf("Indirect write completion error (%i)\n", ret);
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goto failwr;
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}
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@@ -864,7 +784,7 @@ failwr:
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/* Cancel the indirect write */
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writel(CQSPI_REG_INDIRECTWR_CANCEL_MASK,
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plat->regbase + CQSPI_REG_INDIRECTWR);
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- return -1;
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+ return ret;
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}
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void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)
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