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@@ -363,6 +363,12 @@ static phys_size_t sdram_setup(int casl)
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udelay (1000);
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#endif /* CONFIG_TQM8548 */
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+ /*
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+ * get_ram_size() depends on having tlbs for the DDR, but they are
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+ * not yet setup because we don't know the size. Set up a temp
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+ * mapping and delete it when done.
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+ */
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+ setup_ddr_tlbs(CONFIG_SYS_DDR_EARLY_SIZE_MB);
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for (i = 0; i < N_DDR_CS_CONF; i++) {
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ddr->cs0_config = ddr_cs_conf[i].reg;
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@@ -376,6 +382,7 @@ static phys_size_t sdram_setup(int casl)
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break;
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}
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}
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+ clear_ddr_tlbs(CONFIG_SYS_DDR_EARLY_SIZE_MB);
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#ifdef CONFIG_TQM8548
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if (i < N_DDR_CS_CONF) {
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