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@@ -116,6 +116,7 @@
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/* Master trigger */
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#define SFC_DMA_TRIGGER 0x80
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+#define SFC_DMA_TRIGGER_START 1
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/* Src or Dst addr for master */
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#define SFC_DMA_ADDR 0x84
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@@ -163,14 +164,12 @@
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#define SFC_DMA_TRANS_THRETHOLD (0x40)
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/* Maximum clock values from datasheet suggest keeping clock value under
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- * 150MHz. No minimum or average value is suggested, but the U-boot BSP driver
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- * has a minimum of 10MHz and a default of 80MHz which seems reasonable.
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+ * 150MHz. No minimum or average value is suggested.
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*/
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-#define SFC_MIN_SPEED_HZ (10 * 1000 * 1000)
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-#define SFC_DEFAULT_SPEED_HZ (80 * 1000 * 1000)
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-#define SFC_MAX_SPEED_HZ (150 * 1000 * 1000)
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+#define SFC_MAX_SPEED (150 * 1000 * 1000)
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struct rockchip_sfc {
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+ struct udevice *dev;
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void __iomem *regbase;
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struct clk hclk;
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struct clk clk;
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@@ -197,8 +196,6 @@ static int rockchip_sfc_reset(struct rockchip_sfc *sfc)
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/* Still need to clear the masked interrupt from RISR */
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writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
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- debug("reset\n");
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-
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return err;
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}
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@@ -261,15 +258,11 @@ static int rockchip_sfc_probe(struct udevice *bus)
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#if CONFIG_IS_ENABLED(CLK)
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ret = clk_enable(&sfc->hclk);
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if (ret)
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- debug("Enable ahb clock fail %s: %d\n", bus->name, ret);
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+ dev_dbg(sfc->dev, "sfc Enable ahb clock fail %s: %d\n", bus->name, ret);
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ret = clk_enable(&sfc->clk);
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if (ret)
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- debug("Enable clock fail for %s: %d\n", bus->name, ret);
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-
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- ret = clk_set_rate(&sfc->clk, SFC_DEFAULT_SPEED_HZ);
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- if (ret)
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- debug("Could not set sfc clock for %s: %d\n", bus->name, ret);
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+ dev_dbg(sfc->dev, "sfc Enable clock fail for %s: %d\n", bus->name, ret);
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#endif
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ret = rockchip_sfc_init(sfc);
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@@ -278,7 +271,8 @@ static int rockchip_sfc_probe(struct udevice *bus)
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sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc);
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sfc->version = rockchip_sfc_get_version(sfc);
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- sfc->speed = SFC_DEFAULT_SPEED_HZ;
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+ sfc->max_freq = SFC_MAX_SPEED;
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+ sfc->dev = bus;
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return 0;
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@@ -411,11 +405,11 @@ static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc,
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ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE;
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cmd |= plat->cs << SFC_CMD_CS_SHIFT;
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- debug("addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n",
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- op->addr.nbytes, op->addr.buswidth,
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- op->dummy.nbytes, op->dummy.buswidth);
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- debug("ctrl=%x cmd=%x addr=%llx len=%x\n",
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- ctrl, cmd, op->addr.val, len);
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+ dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n",
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+ op->addr.nbytes, op->addr.buswidth,
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+ op->dummy.nbytes, op->dummy.buswidth);
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+ dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x\n",
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+ ctrl, cmd, op->addr.val, len);
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writel(ctrl, sfc->regbase + SFC_CTRL);
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writel(cmd, sfc->regbase + SFC_CMD);
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@@ -492,7 +486,7 @@ static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t d
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{
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writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
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writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR);
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- writel(0x1, sfc->regbase + SFC_DMA_TRIGGER);
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+ writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER);
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return len;
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}
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@@ -500,7 +494,7 @@ static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t d
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static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc,
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const struct spi_mem_op *op, u32 len)
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{
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- debug("xfer_poll len=%x\n", len);
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+ dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len);
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if (op->data.dir == SPI_MEM_DATA_OUT)
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return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len);
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@@ -516,7 +510,7 @@ static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc,
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void *dma_buf;
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int ret;
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- debug("xfer_dma len=%x\n", len);
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+ dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len);
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if (op->data.dir == SPI_MEM_DATA_OUT) {
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dma_buf = (void *)op->data.buf.out;
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@@ -564,33 +558,16 @@ static int rockchip_sfc_exec_op(struct spi_slave *mem,
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u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize);
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int ret;
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-#if CONFIG_IS_ENABLED(CLK)
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- if (unlikely(mem->max_hz != sfc->speed)) {
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- ret = clk_set_rate(&sfc->clk, clamp(mem->max_hz, (uint)SFC_MIN_SPEED_HZ,
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- (uint)SFC_MAX_SPEED_HZ));
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- if (ret < 0) {
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- printf("set_freq=%dHz fail, check if it's the cru support level\n",
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- mem->max_hz);
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- return ret;
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- }
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-
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- sfc->max_freq = mem->max_hz;
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- sfc->speed = mem->max_hz;
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- debug("set_freq=%dHz real_freq=%dHz\n", sfc->max_freq, sfc->speed);
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- }
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-#endif
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-
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rockchip_sfc_adjust_op_work((struct spi_mem_op *)op);
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-
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rockchip_sfc_xfer_setup(sfc, mem, op, len);
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if (len) {
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- if (likely(sfc->use_dma) && !(len & 0x3) && len >= SFC_DMA_TRANS_THRETHOLD)
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+ if (likely(sfc->use_dma) && len >= SFC_DMA_TRANS_THRETHOLD)
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ret = rockchip_sfc_xfer_data_dma(sfc, op, len);
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else
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ret = rockchip_sfc_xfer_data_poll(sfc, op, len);
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if (ret != len) {
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- printf("xfer data failed ret %d dir %d\n", ret, op->data.dir);
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+ dev_err(sfc->dev, "xfer data failed ret %d dir %d\n", ret, op->data.dir);
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return -EIO;
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}
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@@ -604,13 +581,32 @@ static int rockchip_sfc_adjust_op_size(struct spi_slave *mem, struct spi_mem_op
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struct rockchip_sfc *sfc = dev_get_plat(mem->dev->parent);
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op->data.nbytes = min(op->data.nbytes, sfc->max_iosize);
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+
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return 0;
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}
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static int rockchip_sfc_set_speed(struct udevice *bus, uint speed)
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{
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- /* We set up speed later for each transmission.
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- */
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+ struct rockchip_sfc *sfc = dev_get_plat(bus);
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+
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+ if (speed > sfc->max_freq)
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+ speed = sfc->max_freq;
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+
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+ if (speed == sfc->speed)
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+ return 0;
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+
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+#if CONFIG_IS_ENABLED(CLK)
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+ int ret = clk_set_rate(&sfc->clk, speed);
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+
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+ if (ret < 0) {
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+ dev_err(sfc->dev, "set_freq=%dHz fail, check if it's the cru support level\n",
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+ speed);
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+ return ret;
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+ }
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+ sfc->speed = speed;
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+#else
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+ dev_dbg(sfc->dev, "sfc failed, CLK not support\n");
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+#endif
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return 0;
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}
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