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Merge tag 'u-boot-rockchip-20190823' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip

- remove rk3288 fennec board
- remove SPL raw image support for Rockchip SoCs
- add common misc_init_r() for ethaddr from cpuid
- enable USB HOST support for rk3328
- unify code for finding a valid gpt in part driver
Tom Rini 4 years ago
parent
commit
50b4b80f59
56 changed files with 409 additions and 965 deletions
  1. 2 1
      Kconfig
  2. 0 1
      arch/arm/dts/Makefile
  3. 0 54
      arch/arm/dts/rk3288-fennec-u-boot.dtsi
  4. 0 31
      arch/arm/dts/rk3288-fennec.dts
  5. 0 421
      arch/arm/dts/rk3288-fennec.dtsi
  6. 5 26
      arch/arm/dts/rk3328-evb-u-boot.dtsi
  7. 0 5
      arch/arm/dts/rk3328-evb.dts
  8. 5 28
      arch/arm/dts/rk3328-rock64-u-boot.dtsi
  9. 2 21
      arch/arm/dts/rk3328-rock64.dts
  10. 58 0
      arch/arm/dts/rk3328-u-boot.dtsi
  11. 0 24
      arch/arm/dts/rk3328.dtsi
  12. 13 0
      arch/arm/include/asm/arch-rockchip/misc.h
  13. 4 0
      arch/arm/mach-rockchip/Makefile
  14. 23 0
      arch/arm/mach-rockchip/board.c
  15. 114 0
      arch/arm/mach-rockchip/misc.c
  16. 0 2
      arch/arm/mach-rockchip/rk3288/Kconfig
  17. 0 15
      board/rockchip/fennec_rk3288/Kconfig
  18. 0 6
      board/rockchip/fennec_rk3288/MAINTAINERS
  19. 0 7
      board/rockchip/fennec_rk3288/Makefile
  20. 0 5
      board/rockchip/fennec_rk3288/fennec-rk3288.c
  21. 18 90
      board/theobroma-systems/puma_rk3399/puma-rk3399.c
  22. 1 0
      configs/chromebook_bob_defconfig
  23. 1 0
      configs/evb-px5_defconfig
  24. 1 0
      configs/evb-rk3328_defconfig
  25. 1 0
      configs/evb-rk3399_defconfig
  26. 0 84
      configs/fennec-rk3288_defconfig
  27. 1 0
      configs/ficus-rk3399_defconfig
  28. 1 0
      configs/firefly-rk3399_defconfig
  29. 1 0
      configs/khadas-edge-captain-rk3399_defconfig
  30. 1 0
      configs/khadas-edge-rk3399_defconfig
  31. 1 0
      configs/khadas-edge-v-rk3399_defconfig
  32. 1 0
      configs/nanopc-t4-rk3399_defconfig
  33. 1 0
      configs/nanopi-m4-rk3399_defconfig
  34. 1 0
      configs/nanopi-neo4-rk3399_defconfig
  35. 1 0
      configs/orangepi-rk3399_defconfig
  36. 1 0
      configs/roc-rk3399-pc_defconfig
  37. 2 0
      configs/rock-pi-4-rk3399_defconfig
  38. 1 0
      configs/rock64-rk3328_defconfig
  39. 1 0
      configs/rock960-rk3399_defconfig
  40. 1 0
      configs/rockpro64-rk3399_defconfig
  41. 49 40
      disk/part_efi.c
  42. 1 2
      doc/README.rockchip
  43. 12 0
      drivers/clk/rockchip/clk_rk3328.c
  44. 81 78
      drivers/ram/rockchip/sdram_rk3399.c
  45. 1 1
      include/configs/evb_rk3399.h
  46. 0 14
      include/configs/fennec_rk3288.h
  47. 0 1
      include/configs/rk3036_common.h
  48. 0 1
      include/configs/rk3128_common.h
  49. 0 1
      include/configs/rk3188_common.h
  50. 0 1
      include/configs/rk322x_common.h
  51. 0 1
      include/configs/rk3288_common.h
  52. 0 1
      include/configs/rk3328_common.h
  53. 0 1
      include/configs/rk3368_common.h
  54. 0 1
      include/configs/rk3399_common.h
  55. 0 1
      include/configs/rv1108_common.h
  56. 2 0
      include/part_efi.h

+ 2 - 1
Kconfig

@@ -156,7 +156,8 @@ config SYS_MALLOC_F_LEN
 
 config SYS_MALLOC_LEN
 	hex "Define memory for Dynamic allocation"
-	depends on ARCH_ZYNQ || ARCH_VERSAL || ARCH_STM32MP
+	depends on ARCH_ZYNQ || ARCH_VERSAL || ARCH_STM32MP || ARCH_ROCKCHIP
+	default 0x2000000 if ARCH_ROCKCHIP
 	help
 	  This defines memory to be allocated for Dynamic allocation
 	  TODO: Use for other architectures

+ 0 - 1
arch/arm/dts/Makefile

@@ -81,7 +81,6 @@ dtb-$(CONFIG_ROCKCHIP_RK322X) += \
 
 dtb-$(CONFIG_ROCKCHIP_RK3288) += \
 	rk3288-evb.dtb \
-	rk3288-fennec.dtb \
 	rk3288-firefly.dtb \
 	rk3288-miqi.dtb \
 	rk3288-phycore-rdk.dtb \

+ 0 - 54
arch/arm/dts/rk3288-fennec-u-boot.dtsi

@@ -1,54 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2019 Rockchip Electronics Co., Ltd
- */
-
-#include "rk3288-u-boot.dtsi"
-
-&pinctrl {
-	u-boot,dm-pre-reloc;
-};
-
-&uart2 {
-	u-boot,dm-pre-reloc;
-};
-
-&sdmmc {
-	u-boot,dm-pre-reloc;
-};
-
-&emmc {
-	u-boot,dm-pre-reloc;
-};
-
-&gpio3 {
-	u-boot,dm-pre-reloc;
-};
-
-&gpio8 {
-	u-boot,dm-pre-reloc;
-};
-
-&pcfg_pull_none_drv_8ma {
-	u-boot,dm-spl;
-};
-
-&pcfg_pull_up_drv_8ma {
-	u-boot,dm-spl;
-};
-
-&sdmmc_bus4 {
-	u-boot,dm-spl;
-};
-
-&sdmmc_clk {
-	u-boot,dm-spl;
-};
-
-&sdmmc_cmd {
-	u-boot,dm-spl;
-};
-
-&sdmmc_pwr {
-	u-boot,dm-spl;
-};

+ 0 - 31
arch/arm/dts/rk3288-fennec.dts

@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR X11
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- */
-
-/dts-v1/;
-#include "rk3288-fennec.dtsi"
-
-/ {
-	model = "Rockchip RK3288 Fennec Board";
-	compatible = "rockchip,rk3288-fennec", "rockchip,rk3288";
-
-	chosen {
-		stdout-path = &uart2;
-	};
-};
-
-&dmc {
-	rockchip,pctl-timing = <0x215 0xc8 0x0 0x35 0x26 0x2 0x70 0x2000d
-		0x6 0x0 0x8 0x4 0x17 0x24 0xd 0x6
-		0x4 0x8 0x4 0x76 0x4 0x0 0x30 0x0
-		0x1 0x2 0x2 0x4 0x0 0x0 0xc0 0x4
-		0x8 0x1f4>;
-	rockchip,phy-timing = <0x48d7dd93 0x187008d8 0x121076
-		0x0 0xc3 0x6 0x2>;
-	rockchip,sdram-params = <0x20d266a4 0x5b6 2 533000000 6 9 0>;
-};
-
-&pwm1 {
-	status = "okay";
-};

+ 0 - 421
arch/arm/dts/rk3288-fennec.dtsi

@@ -1,421 +0,0 @@
-/*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "rk3288.dtsi"
-
-/ {
-	memory {
-		reg = <0x0 0x80000000>;
-		device_type = "memory";
-	};
-
-	ext_gmac: external-gmac-clock {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <125000000>;
-		clock-output-names = "ext_gmac";
-	};
-
-	vcc_sys: vsys-regulator {
-		compatible = "regulator-fixed";
-		regulator-name = "vcc_sys";
-		regulator-min-microvolt = <5000000>;
-		regulator-max-microvolt = <5000000>;
-		regulator-always-on;
-		regulator-boot-on;
-	};
-};
-
-&cpu0 {
-	cpu0-supply = <&vdd_cpu>;
-};
-
-&emmc {
-	bus-width = <8>;
-	cap-mmc-highspeed;
-	disable-wp;
-	non-removable;
-	num-slots = <1>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_pwr &emmc_bus8>;
-	status = "okay";
-};
-
-&sdmmc {
-	bus-width = <4>;
-	cap-mmc-highspeed;
-	cap-sd-highspeed;
-	card-detect-delay = <200>;
-	disable-wp;
-	num-slots = <1>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
-	status = "okay";
-	vmmc-supply = <&vcc_sd>;
-	vqmmc-supply = <&vccio_sd>;
-};
-
-&gmac {
-	assigned-clocks = <&cru SCLK_MAC>;
-	assigned-clock-parents = <&ext_gmac>;
-	clock_in_out = "input";
-	pinctrl-names = "default";
-	pinctrl-0 = <&rgmii_pins>, <&phy_rst>, <&phy_pmeb>, <&phy_int>;
-	phy-supply = <&vcc_lan>;
-	phy-mode = "rgmii";
-	snps,reset-active-low;
-	snps,reset-delays-us = <0 10000 1000000>;
-	snps,reset-gpio = <&gpio4 8 GPIO_ACTIVE_LOW>;
-	tx_delay = <0x30>;
-	rx_delay = <0x10>;
-	status = "okay";
-};
-
-&gpu {
-	mali-supply = <&vdd_gpu>;
-	status = "okay";
-};
-
-&hdmi {
-	status = "okay";
-};
-
-&i2c0 {
-	status = "okay";
-	clock-frequency = <400000>;
-
-	rk808: pmic@1b {
-		compatible = "rockchip,rk808";
-		reg = <0x1b>;
-		interrupt-parent = <&gpio0>;
-		interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
-		#clock-cells = <1>;
-		clock-output-names = "xin32k", "rk808-clkout2";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pmic_int &global_pwroff>;
-		rockchip,system-power-controller;
-		wakeup-source;
-
-		vcc1-supply = <&vcc_sys>;
-		vcc2-supply = <&vcc_sys>;
-		vcc3-supply = <&vcc_sys>;
-		vcc4-supply = <&vcc_sys>;
-		vcc6-supply = <&vcc_sys>;
-		vcc7-supply = <&vcc_sys>;
-		vcc8-supply = <&vcc_io>;
-		vcc9-supply = <&vcc_io>;
-		vcc10-supply = <&vcc_io>;
-		vcc11-supply = <&vcc_io>;
-		vcc12-supply = <&vcc_io>;
-		vddio-supply = <&vcc_io>;
-
-		regulators {
-			vdd_cpu: DCDC_REG1 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <750000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-name = "vdd_arm";
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_gpu: DCDC_REG2 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <850000>;
-				regulator-max-microvolt = <1250000>;
-				regulator-name = "vdd_gpu";
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1000000>;
-				};
-			};
-
-			vcc_ddr: DCDC_REG3 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-name = "vcc_ddr";
-				regulator-state-mem {
-					regulator-on-in-suspend;
-				};
-			};
-
-			vcc_io: DCDC_REG4 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-name = "vcc_io";
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <3300000>;
-				};
-			};
-
-			vccio_pmu: LDO_REG1 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-name = "vccio_pmu";
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <3300000>;
-				};
-			};
-
-			vcca_33: LDO_REG2 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <3300000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-name = "vcca_33";
-				regulator-state-mem {
-					regulator-off-in-suspend;
-				};
-			};
-
-			vdd_10: LDO_REG3 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1000000>;
-				regulator-max-microvolt = <1000000>;
-				regulator-name = "vdd_10";
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1000000>;
-				};
-			};
-
-			vcc_wl: LDO_REG4 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-name = "vcc_wl";
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			vccio_sd: LDO_REG5 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-name = "vccio_sd";
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <3300000>;
-				};
-			};
-
-			vdd10_lcd: LDO_REG6 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1000000>;
-				regulator-max-microvolt = <1000000>;
-				regulator-name = "vdd10_lcd";
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1000000>;
-				};
-			};
-
-			vcc_18: LDO_REG7 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-name = "vcc_18";
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			vcc18_lcd: LDO_REG8 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-name = "vcc18_lcd";
-				regulator-state-mem {
-					regulator-on-in-suspend;
-					regulator-suspend-microvolt = <1800000>;
-				};
-			};
-
-			vcc_sd: SWITCH_REG1 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-name = "vcc_sd";
-				regulator-state-mem {
-					regulator-on-in-suspend;
-				};
-			};
-
-			vcc_lan: SWITCH_REG2 {
-				regulator-always-on;
-				regulator-boot-on;
-				regulator-name = "vcc_lan";
-				regulator-state-mem {
-					regulator-on-in-suspend;
-				};
-			};
-		};
-	};
-};
-
-&pinctrl {
-	pcfg_output_high: pcfg-output-high {
-		output-high;
-	};
-
-	pcfg_output_low: pcfg-output-low {
-		output-low;
-	};
-
-	pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
-		drive-strength = <8>;
-	};
-
-	pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
-		bias-pull-up;
-		drive-strength = <8>;
-	};
-
-	gmac {
-		phy_int: phy-int {
-			rockchip,pins = <0 9 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-
-		phy_pmeb: phy-pmeb {
-			rockchip,pins = <0 8 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-
-		phy_rst: phy-rst {
-			rockchip,pins = <4 8 RK_FUNC_GPIO &pcfg_output_high>;
-		};
-	};
-
-	pmic {
-		pmic_int: pmic-int {
-			rockchip,pins = <RK_GPIO0 4 RK_FUNC_GPIO &pcfg_pull_up>;
-		};
-	};
-
-	sdmmc {
-		sdmmc_bus4: sdmmc-bus4 {
-			rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
-					<6 17 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
-					<6 18 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
-					<6 19 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
-		};
-
-		sdmmc_clk: sdmmc-clk {
-			rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none_drv_8ma>;
-		};
-
-		sdmmc_cmd: sdmmc-cmd {
-			rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
-		};
-
-		sdmmc_pwr: sdmmc-pwr {
-			rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-
-	usbphy {
-		host_drv: host-drv {
-			rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
-};
-
-&uart2 {
-	status = "okay";
-};
-
-&usbphy {
-	pinctrl-names = "default";
-	pinctrl-0 = <&host_drv>;
-	vbus_drv-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
-	status = "okay";
-};
-
-&usb_host0_ehci {
-	status = "okay";
-};
-
-&usb_host1 {
-	status = "okay";
-};
-
-&usb_otg {
-	status = "okay";
-};
-
-&usb_hsic {
-	status = "okay";
-};
-
-&vopb {
-	status = "okay";
-};
-
-&vopb_mmu {
-	status = "okay";
-};
-
-&vopl {
-	status = "okay";
-};
-
-&vopl_mmu {
-	status = "okay";
-};
-
-&vpu {
-	status = "okay";
-};

+ 5 - 26
arch/arm/dts/rk3328-evb-u-boot.dtsi

@@ -1,33 +1,12 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
+ * (C) Copyright 2016-2019 Rockchip Electronics Co., Ltd
  */
 
+#include "rk3328-u-boot.dtsi"
 #include "rk3328-sdram-ddr3-666.dtsi"
 
-/ {
-	aliases {
-		mmc0 = &emmc;
-		mmc1 = &sdmmc;
-	};
-
-	chosen {
-		u-boot,spl-boot-order = &emmc, &sdmmc;
-	};
-};
-
-&cru {
-	u-boot,dm-pre-reloc;
-};
-
-&uart2 {
-	u-boot,dm-pre-reloc;
-};
-
-&emmc {
-	u-boot,dm-pre-reloc;
-};
-
-&sdmmc {
-	u-boot,dm-pre-reloc;
+&usb_host0_xhci {
+	vbus-supply = <&vcc5v0_host_xhci>;
+	status = "okay";
 };

+ 0 - 5
arch/arm/dts/rk3328-evb.dts

@@ -116,11 +116,6 @@
 	status = "okay";
 };
 
-&usb_host0_xhci {
-	vbus-supply = <&vcc5v0_host_xhci>;
-	status = "okay";
-};
-
 &i2c1 {
 	clock-frequency = <400000>;
 	i2c-scl-rising-time-ns = <168>;

+ 5 - 28
arch/arm/dts/rk3328-rock64-u-boot.dtsi

@@ -1,34 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
- * (C) Copyright 2018 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier:     GPL-2.0+
+ * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
  */
 
+#include "rk3328-u-boot.dtsi"
 #include "rk3328-sdram-lpddr3-1600.dtsi"
 
-/ {
-	aliases {
-		mmc0 = &emmc;
-		mmc1 = &sdmmc;
-	};
-
-	chosen {
-		u-boot,spl-boot-order = &emmc, &sdmmc;
-	};
-};
-
-&cru {
-	u-boot,dm-pre-reloc;
-};
-
-&uart2 {
-	u-boot,dm-pre-reloc;
-};
-
-&emmc {
-	u-boot,dm-pre-reloc;
-};
-
-&sdmmc {
-	u-boot,dm-pre-reloc;
+&usb_host0_xhci {
+	status = "okay";
 };

+ 2 - 21
arch/arm/dts/rk3328-rock64.dts

@@ -34,23 +34,10 @@
 
 	vcc_host_5v: vcc-host-5v-regulator {
 		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&usb30_host_drv>;
-		regulator-name = "vcc_host_5v";
-		regulator-always-on;
-		regulator-boot-on;
-		vin-supply = <&vcc_sys>;
-	};
-
-	vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
-		compatible = "regulator-fixed";
-		enable-active-high;
-		gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+		gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&usb20_host_drv>;
-		regulator-name = "vcc_host1_5v";
+		regulator-name = "vcc_host_5v";
 		regulator-always-on;
 		regulator-boot-on;
 		vin-supply = <&vcc_sys>;
@@ -244,12 +231,6 @@
 			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
 		};
 	};
-
-	usb3 {
-		usb30_host_drv: usb30-host-drv {
-			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
-		};
-	};
 };
 
 &sdmmc {

+ 58 - 0
arch/arm/dts/rk3328-u-boot.dtsi

@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+/ {
+	aliases {
+		mmc0 = &emmc;
+		mmc1 = &sdmmc;
+	};
+
+	chosen {
+		u-boot,spl-boot-order = &emmc, &sdmmc;
+	};
+
+	dmc: dmc {
+		u-boot,dm-pre-reloc;
+		compatible = "rockchip,rk3328-dmc";
+		reg = <0x0 0xff400000 0x0 0x1000
+		       0x0 0xff780000 0x0 0x3000
+		       0x0 0xff100000 0x0 0x1000
+		       0x0 0xff440000 0x0 0x1000
+		       0x0 0xff720000 0x0 0x1000
+		       0x0 0xff798000 0x0 0x1000>;
+	};
+
+	usb_host0_xhci: usb@ff600000 {
+		compatible = "rockchip,rk3328-xhci";
+		reg = <0x0 0xff600000 0x0 0x100000>;
+		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+		snps,dis-enblslpm-quirk;
+		snps,phyif-utmi-bits = <16>;
+		snps,dis-u2-freeclk-exists-quirk;
+		snps,dis-u2-susphy-quirk;
+		status = "disabled";
+	};
+};
+
+&cru {
+	u-boot,dm-pre-reloc;
+};
+
+&grf {
+	u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+	u-boot,dm-pre-reloc;
+	clock-frequency = <24000000>;
+};
+
+&emmc {
+	u-boot,dm-pre-reloc;
+};
+
+&sdmmc {
+	u-boot,dm-pre-reloc;
+};

+ 0 - 24
arch/arm/dts/rk3328.dtsi

@@ -186,7 +186,6 @@
 	};
 
 	grf: syscon@ff100000 {
-		u-boot,dm-pre-reloc;
 		compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
 		reg = <0x0 0xff100000 0x0 0x1000>;
 
@@ -232,7 +231,6 @@
 		interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 		clock-names = "baudclk", "apb_pclk";
-		clock-frequency = <24000000>;
 		reg-shift = <2>;
 		reg-io-width = <4>;
 		dmas = <&dmac 6>, <&dmac 7>;
@@ -351,17 +349,6 @@
 		status = "disabled";
 	};
 
-	dmc: dmc {
-		u-boot,dm-pre-reloc;
-		compatible = "rockchip,rk3328-dmc";
-		reg = <0x0 0xff400000 0x0 0x1000
-		       0x0 0xff780000 0x0 0x3000
-		       0x0 0xff100000 0x0 0x1000
-		       0x0 0xff440000 0x0 0x1000
-		       0x0 0xff720000 0x0 0x1000
-		       0x0 0xff798000 0x0 0x1000>;
-	};
-
 	cru: clock-controller@ff440000 {
 		compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
 		reg = <0x0 0xff440000 0x0 0x1000>;
@@ -512,17 +499,6 @@
 		status = "disabled";
 	};
 
-	usb_host0_xhci: usb@ff600000 {
-		compatible = "rockchip,rk3328-xhci";
-		reg = <0x0 0xff600000 0x0 0x100000>;
-		interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
-		snps,dis-enblslpm-quirk;
-		snps,phyif-utmi-bits = <16>;
-		snps,dis-u2-freeclk-exists-quirk;
-		snps,dis-u2-susphy-quirk;
-		status = "disabled";
-	};
-
 	gic: interrupt-controller@ffb70000 {
 		compatible = "arm,gic-400";
 		#interrupt-cells = <3>;

+ 13 - 0
arch/arm/include/asm/arch-rockchip/misc.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * RK3399: Architecture common definitions
+ *
+ * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/
+ *      Rohan Garg <rohan.garg@collabora.com>
+ */
+
+int rockchip_cpuid_from_efuse(const u32 cpuid_offset,
+			      const u32 cpuid_length,
+			      u8 *cpuid);
+int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length);
+int rockchip_setup_macaddr(void);

+ 4 - 0
arch/arm/mach-rockchip/Makefile

@@ -25,6 +25,10 @@ endif
 
 obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram_common.o
 
+ifdef CONFIG_MISC_INIT_R
+obj-y += misc.o
+endif
+
 obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
 obj-$(CONFIG_ROCKCHIP_RK3128) += rk3128/
 ifndef CONFIG_TPL_BUILD

+ 23 - 0
arch/arm/mach-rockchip/board.c

@@ -11,6 +11,7 @@
 #include <asm/arch-rockchip/boot_mode.h>
 #include <asm/arch-rockchip/clock.h>
 #include <asm/arch-rockchip/periph.h>
+#include <asm/arch-rockchip/misc.h>
 #include <power/regulator.h>
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -102,3 +103,25 @@ int fastboot_set_reboot_flag(void)
 	return 0;
 }
 #endif
+
+#ifdef CONFIG_MISC_INIT_R
+__weak int misc_init_r(void)
+{
+	const u32 cpuid_offset = 0x7;
+	const u32 cpuid_length = 0x10;
+	u8 cpuid[cpuid_length];
+	int ret;
+
+	ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
+	if (ret)
+		return ret;
+
+	ret = rockchip_cpuid_set(cpuid, cpuid_length);
+	if (ret)
+		return ret;
+
+	ret = rockchip_setup_macaddr();
+
+	return ret;
+}
+#endif

+ 114 - 0
arch/arm/mach-rockchip/misc.c

@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * RK3399: Architecture common definitions
+ *
+ * Copyright (C) 2019 Collabora Inc - https://www.collabora.com/
+ *      Rohan Garg <rohan.garg@collabora.com>
+ *
+ * Based on puma-rk3399.c:
+ *      (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ */
+
+#include <common.h>
+#include <env.h>
+#include <dm.h>
+#include <dm/uclass-internal.h>
+#include <misc.h>
+#include <u-boot/sha256.h>
+
+#include <asm/arch-rockchip/misc.h>
+
+int rockchip_setup_macaddr(void)
+{
+#if CONFIG_IS_ENABLED(CMD_NET)
+	int ret;
+	const char *cpuid = env_get("cpuid#");
+	u8 hash[SHA256_SUM_LEN];
+	int size = sizeof(hash);
+	u8 mac_addr[6];
+
+	/* Only generate a MAC address, if none is set in the environment */
+	if (env_get("ethaddr"))
+		return -1;
+
+	if (!cpuid) {
+		debug("%s: could not retrieve 'cpuid#'\n", __func__);
+		return -1;
+	}
+
+	ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size);
+	if (ret) {
+		debug("%s: failed to calculate SHA256\n", __func__);
+		return -1;
+	}
+
+	/* Copy 6 bytes of the hash to base the MAC address on */
+	memcpy(mac_addr, hash, 6);
+
+	/* Make this a valid MAC address and set it */
+	mac_addr[0] &= 0xfe;  /* clear multicast bit */
+	mac_addr[0] |= 0x02;  /* set local assignment bit (IEEE802) */
+	eth_env_set_enetaddr("ethaddr", mac_addr);
+#endif
+	return 0;
+}
+
+int rockchip_cpuid_from_efuse(const u32 cpuid_offset,
+			      const u32 cpuid_length,
+			      u8 *cpuid)
+{
+#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE)
+	struct udevice *dev;
+	int ret;
+
+	/* retrieve the device */
+	ret = uclass_get_device_by_driver(UCLASS_MISC,
+					  DM_GET_DRIVER(rockchip_efuse), &dev);
+	if (ret) {
+		debug("%s: could not find efuse device\n", __func__);
+		return -1;
+	}
+
+	/* read the cpu_id range from the efuses */
+	ret = misc_read(dev, cpuid_offset, cpuid, sizeof(cpuid));
+	if (ret) {
+		debug("%s: reading cpuid from the efuses failed\n",
+		      __func__);
+		return -1;
+	}
+#endif
+	return 0;
+}
+
+int rockchip_cpuid_set(const u8 *cpuid, const u32 cpuid_length)
+{
+	u8 low[cpuid_length / 2], high[cpuid_length / 2];
+	char cpuid_str[cpuid_length * 2 + 1];
+	u64 serialno;
+	char serialno_str[17];
+	int i;
+
+	memset(cpuid_str, 0, sizeof(cpuid_str));
+	for (i = 0; i < 16; i++)
+		sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]);
+
+	debug("cpuid: %s\n", cpuid_str);
+
+	/*
+	 * Mix the cpuid bytes using the same rules as in
+	 *   ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c
+	 */
+	for (i = 0; i < 8; i++) {
+		low[i] = cpuid[1 + (i << 1)];
+		high[i] = cpuid[i << 1];
+	}
+
+	serialno = crc32_no_comp(0, low, 8);
+	serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32;
+	snprintf(serialno_str, sizeof(serialno_str), "%016llx", serialno);
+
+	env_set("cpuid#", cpuid_str);
+	env_set("serial#", serialno_str);
+
+	return 0;
+}

+ 0 - 2
arch/arm/mach-rockchip/rk3288/Kconfig

@@ -191,8 +191,6 @@ source "board/radxa/rock2/Kconfig"
 
 source "board/rockchip/evb_rk3288/Kconfig"
 
-source "board/rockchip/fennec_rk3288/Kconfig"
-
 source "board/rockchip/tinker_rk3288/Kconfig"
 
 endif

+ 0 - 15
board/rockchip/fennec_rk3288/Kconfig

@@ -1,15 +0,0 @@
-if TARGET_FENNEC_RK3288
-
-config SYS_BOARD
-	default "fennec_rk3288"
-
-config SYS_VENDOR
-	default "rockchip"
-
-config SYS_CONFIG_NAME
-	default "fennec_rk3288"
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-
-endif

+ 0 - 6
board/rockchip/fennec_rk3288/MAINTAINERS

@@ -1,6 +0,0 @@
-FENNEC-RK3288
-M:	Lin Huang <hl@rock-chips.com>
-S:	Maintained
-F:	board/rockchip/fennec_rk3288
-F:	include/configs/fennec_rk3288.h
-F:	configs/fennec-rk3288_defconfig

+ 0 - 7
board/rockchip/fennec_rk3288/Makefile

@@ -1,7 +0,0 @@
-#
-# (C) Copyright 2016 Rockchip Electronics Co., Ltd
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y	+= fennec-rk3288.o

+ 0 - 5
board/rockchip/fennec_rk3288/fennec-rk3288.c

@@ -1,5 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- */
-

+ 18 - 90
board/theobroma-systems/puma_rk3399/puma-rk3399.c

@@ -18,97 +18,10 @@
 #include <asm/arch-rockchip/hardware.h>
 #include <asm/arch-rockchip/grf_rk3399.h>
 #include <asm/arch-rockchip/periph.h>
+#include <asm/arch-rockchip/misc.h>
 #include <power/regulator.h>
 #include <u-boot/sha256.h>
 
-static void setup_macaddr(void)
-{
-#if CONFIG_IS_ENABLED(CMD_NET)
-	int ret;
-	const char *cpuid = env_get("cpuid#");
-	u8 hash[SHA256_SUM_LEN];
-	int size = sizeof(hash);
-	u8 mac_addr[6];
-
-	/* Only generate a MAC address, if none is set in the environment */
-	if (env_get("ethaddr"))
-		return;
-
-	if (!cpuid) {
-		debug("%s: could not retrieve 'cpuid#'\n", __func__);
-		return;
-	}
-
-	ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size);
-	if (ret) {
-		debug("%s: failed to calculate SHA256\n", __func__);
-		return;
-	}
-
-	/* Copy 6 bytes of the hash to base the MAC address on */
-	memcpy(mac_addr, hash, 6);
-
-	/* Make this a valid MAC address and set it */
-	mac_addr[0] &= 0xfe;  /* clear multicast bit */
-	mac_addr[0] |= 0x02;  /* set local assignment bit (IEEE802) */
-	eth_env_set_enetaddr("ethaddr", mac_addr);
-#endif
-}
-
-static void setup_serial(void)
-{
-#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE)
-	const u32 cpuid_offset = 0x7;
-	const u32 cpuid_length = 0x10;
-
-	struct udevice *dev;
-	int ret, i;
-	u8 cpuid[cpuid_length];
-	u8 low[cpuid_length/2], high[cpuid_length/2];
-	char cpuid_str[cpuid_length * 2 + 1];
-	u64 serialno;
-	char serialno_str[17];
-
-	/* retrieve the device */
-	ret = uclass_get_device_by_driver(UCLASS_MISC,
-					  DM_GET_DRIVER(rockchip_efuse), &dev);
-	if (ret) {
-		debug("%s: could not find efuse device\n", __func__);
-		return;
-	}
-
-	/* read the cpu_id range from the efuses */
-	ret = misc_read(dev, cpuid_offset, &cpuid, sizeof(cpuid));
-	if (ret) {
-		debug("%s: reading cpuid from the efuses failed\n",
-		      __func__);
-		return;
-	}
-
-	memset(cpuid_str, 0, sizeof(cpuid_str));
-	for (i = 0; i < 16; i++)
-		sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]);
-
-	debug("cpuid: %s\n", cpuid_str);
-
-	/*
-	 * Mix the cpuid bytes using the same rules as in
-	 *   ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c
-	 */
-	for (i = 0; i < 8; i++) {
-		low[i] = cpuid[1 + (i << 1)];
-		high[i] = cpuid[i << 1];
-	}
-
-	serialno = crc32_no_comp(0, low, 8);
-	serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32;
-	snprintf(serialno_str, sizeof(serialno_str), "%016llx", serialno);
-
-	env_set("cpuid#", cpuid_str);
-	env_set("serial#", serialno_str);
-#endif
-}
-
 static void setup_iodomain(void)
 {
 	const u32 GRF_IO_VSEL_GPIO4CD_SHIFT = 3;
@@ -198,8 +111,23 @@ static int setup_boottargets(void)
 
 int misc_init_r(void)
 {
-	setup_serial();
-	setup_macaddr();
+       const u32 cpuid_offset = 0x7;
+       const u32 cpuid_length = 0x10;
+       u8 cpuid[cpuid_length];
+       int ret;
+
+       ret = rockchip_cpuid_from_efuse(cpuid_offset, cpuid_length, cpuid);
+       if (ret)
+               return ret;
+
+       ret = rockchip_cpuid_set(cpuid, cpuid_length);
+       if (ret)
+               return ret;
+
+       ret = rockchip_setup_macaddr();
+       if (ret)
+               return ret;
+
 	setup_iodomain();
 	setup_boottargets();
 

+ 1 - 0
configs/chromebook_bob_defconfig

@@ -18,6 +18,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-gru-bob.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_TEXT_BASE=0xff8c2000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
 CONFIG_SPL_SPI_LOAD=y

+ 1 - 0
configs/evb-px5_defconfig

@@ -29,6 +29,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3368-px5-evb.dtb"
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_ARCH_EARLY_INIT_R=y
 CONFIG_SPL_BOOTROM_SUPPORT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_TPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_ATF=y

+ 1 - 0
configs/evb-rk3328_defconfig

@@ -20,6 +20,7 @@ CONFIG_SPL_LOAD_FIT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-evb.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_TPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
 CONFIG_TPL_DRIVERS_MISC_SUPPORT=y

+ 1 - 0
configs/evb-rk3399_defconfig

@@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-evb.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
 CONFIG_TPL=y

+ 0 - 84
configs/fennec-rk3288_defconfig

@@ -1,84 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_ROCKCHIP=y
-CONFIG_SYS_TEXT_BASE=0x00000000
-CONFIG_ROCKCHIP_RK3288=y
-CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
-CONFIG_TARGET_FENNEC_RK3288=y
-CONFIG_NR_DRAM_BANKS=1
-CONFIG_SPL_STACK_R_ADDR=0x80000
-CONFIG_DEBUG_UART_BASE=0xff690000
-CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART=y
-# CONFIG_ANDROID_BOOT_IMAGE is not set
-CONFIG_USE_PREBOOT=y
-CONFIG_SILENT_CONSOLE=y
-CONFIG_CONSOLE_MUX=y
-CONFIG_DEFAULT_FDT_FILE="rk3288-fennec.dtb"
-# CONFIG_DISPLAY_CPUINFO is not set
-CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_SPL_TEXT_BASE=0xff704000
-CONFIG_SPL_STACK_R=y
-CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_SF=y
-CONFIG_CMD_SPI=y
-CONFIG_CMD_USB=y
-CONFIG_CMD_USB_MASS_STORAGE=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_CACHE=y
-CONFIG_CMD_TIME=y
-CONFIG_CMD_PMIC=y
-CONFIG_CMD_REGULATOR=y
-# CONFIG_SPL_DOS_PARTITION is not set
-# CONFIG_SPL_EFI_PARTITION is not set
-CONFIG_SPL_PARTITION_UUIDS=y
-CONFIG_SPL_OF_CONTROL=y
-CONFIG_DEFAULT_DEVICE_TREE="rk3288-fennec"
-CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_REGMAP=y
-CONFIG_SPL_REGMAP=y
-CONFIG_SYSCON=y
-CONFIG_SPL_SYSCON=y
-# CONFIG_SPL_SIMPLE_BUS is not set
-CONFIG_CLK=y
-CONFIG_SPL_CLK=y
-CONFIG_FASTBOOT_FLASH=y
-CONFIG_FASTBOOT_FLASH_MMC_DEV=0
-CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_ROCKCHIP_GPIO=y
-CONFIG_SYS_I2C_ROCKCHIP=y
-CONFIG_MMC_DW=y
-CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_SPI_FLASH=y
-CONFIG_SF_DEFAULT_SPEED=20000000
-CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
-CONFIG_GMAC_ROCKCHIP=y
-CONFIG_PINCTRL=y
-CONFIG_SPL_PINCTRL=y
-CONFIG_DM_PMIC=y
-CONFIG_PMIC_RK8XX=y
-CONFIG_DM_REGULATOR_FIXED=y
-CONFIG_REGULATOR_RK8XX=y
-CONFIG_PWM_ROCKCHIP=y
-CONFIG_RAM=y
-CONFIG_SPL_RAM=y
-CONFIG_DEBUG_UART_SHIFT=2
-CONFIG_SYSRESET=y
-CONFIG_USB=y
-CONFIG_USB_DWC2=y
-CONFIG_ROCKCHIP_USB2_PHY=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
-CONFIG_USB_GADGET_VENDOR_NUM=0x2207
-CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
-CONFIG_USB_GADGET_DWC2_OTG=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_ASIX=y
-CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_CMD_DHRYSTONE=y
-CONFIG_ERRNO_STR=y

+ 1 - 0
configs/ficus-rk3399_defconfig

@@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_TEXT_BASE=0xff8c2000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
 CONFIG_CMD_BOOTZ=y

+ 1 - 0
configs/firefly-rk3399_defconfig

@@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-firefly.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
 CONFIG_TPL=y

+ 1 - 0
configs/khadas-edge-captain-rk3399_defconfig

@@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-captain.dtbi"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
 CONFIG_TPL=y

+ 1 - 0
configs/khadas-edge-rk3399_defconfig

@@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
 CONFIG_TPL=y

+ 1 - 0
configs/khadas-edge-v-rk3399_defconfig

@@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-khadas-edge-v.dtbi"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
 CONFIG_TPL=y

+ 1 - 0
configs/nanopc-t4-rk3399_defconfig

@@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopc-t4.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
 CONFIG_TPL=y

+ 1 - 0
configs/nanopi-m4-rk3399_defconfig

@@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
 CONFIG_TPL=y

+ 1 - 0
configs/nanopi-neo4-rk3399_defconfig

@@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-neo4.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
 CONFIG_TPL=y

+ 1 - 0
configs/orangepi-rk3399_defconfig

@@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-orangepi.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
 CONFIG_TPL=y

+ 1 - 0
configs/roc-rk3399-pc_defconfig

@@ -14,6 +14,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-roc-pc.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
 CONFIG_CMD_BOOTZ=y

+ 2 - 0
configs/rock-pi-4-rk3399_defconfig

@@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock-pi-4.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
 CONFIG_TPL=y
@@ -55,3 +56,4 @@ CONFIG_USB_ETHER_RTL8152=y
 CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_SPL_TINY_MEMSET=y
 CONFIG_ERRNO_STR=y
+CONFIG_MISC_INIT_R=y

+ 1 - 0
configs/rock64-rk3328_defconfig

@@ -21,6 +21,7 @@ CONFIG_SPL_LOAD_FIT=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_TPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_ATF=y

+ 1 - 0
configs/rock960-rk3399_defconfig

@@ -12,6 +12,7 @@ CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rock960.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
 CONFIG_SPL_TEXT_BASE=0xff8c2000
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x4000
 CONFIG_SYS_PROMPT="rock960 => "

+ 1 - 0
configs/rockpro64-rk3399_defconfig

@@ -11,6 +11,7 @@ CONFIG_DEBUG_UART=y
 CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-rockpro64.dtb"
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000
 CONFIG_TPL=y

+ 49 - 40
disk/part_efi.c

@@ -51,6 +51,8 @@ static int is_gpt_valid(struct blk_desc *dev_desc, u64 lba,
 static gpt_entry *alloc_read_gpt_entries(struct blk_desc *dev_desc,
 					 gpt_header *pgpt_head);
 static int is_pte_valid(gpt_entry * pte);
+static int find_valid_gpt(struct blk_desc *dev_desc, gpt_header *gpt_head,
+			  gpt_entry **pgpt_pte);
 
 static char *print_efiname(gpt_entry *pte)
 {
@@ -192,19 +194,8 @@ int get_disk_guid(struct blk_desc * dev_desc, char *guid)
 	unsigned char *guid_bin;
 
 	/* This function validates AND fills in the GPT header and PTE */
-	if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
-			 gpt_head, &gpt_pte) != 1) {
-		printf("%s: *** ERROR: Invalid GPT ***\n", __func__);
-		if (is_gpt_valid(dev_desc, dev_desc->lba - 1,
-				 gpt_head, &gpt_pte) != 1) {
-			printf("%s: *** ERROR: Invalid Backup GPT ***\n",
-			       __func__);
-			return -EINVAL;
-		} else {
-			printf("%s: ***        Using Backup GPT ***\n",
-			       __func__);
-		}
-	}
+	if (find_valid_gpt(dev_desc, gpt_head, &gpt_pte) != 1)
+		return -EINVAL;
 
 	guid_bin = gpt_head->disk_guid.b;
 	uuid_bin_to_str(guid_bin, guid, UUID_STR_FORMAT_GUID);
@@ -223,19 +214,8 @@ void part_print_efi(struct blk_desc *dev_desc)
 	unsigned char *uuid_bin;
 
 	/* This function validates AND fills in the GPT header and PTE */
-	if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
-			 gpt_head, &gpt_pte) != 1) {
-		printf("%s: *** ERROR: Invalid GPT ***\n", __func__);
-		if (is_gpt_valid(dev_desc, (dev_desc->lba - 1),
-				 gpt_head, &gpt_pte) != 1) {
-			printf("%s: *** ERROR: Invalid Backup GPT ***\n",
-			       __func__);
-			return;
-		} else {
-			printf("%s: ***        Using Backup GPT ***\n",
-			       __func__);
-		}
-	}
+	if (find_valid_gpt(dev_desc, gpt_head, &gpt_pte) != 1)
+		return;
 
 	debug("%s: gpt-entry at %p\n", __func__, gpt_pte);
 
@@ -284,19 +264,8 @@ int part_get_info_efi(struct blk_desc *dev_desc, int part,
 	}
 
 	/* This function validates AND fills in the GPT header and PTE */
-	if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
-			gpt_head, &gpt_pte) != 1) {
-		printf("%s: *** ERROR: Invalid GPT ***\n", __func__);
-		if (is_gpt_valid(dev_desc, (dev_desc->lba - 1),
-				 gpt_head, &gpt_pte) != 1) {
-			printf("%s: *** ERROR: Invalid Backup GPT ***\n",
-			       __func__);
-			return -1;
-		} else {
-			printf("%s: ***        Using Backup GPT ***\n",
-			       __func__);
-		}
-	}
+	if (find_valid_gpt(dev_desc, gpt_head, &gpt_pte) != 1)
+		return -1;
 
 	if (part > le32_to_cpu(gpt_head->num_partition_entries) ||
 	    !is_pte_valid(&gpt_pte[part - 1])) {
@@ -939,7 +908,7 @@ static int is_pmbr_valid(legacy_mbr * mbr)
  * gpt is a GPT header ptr, filled on return.
  * ptes is a PTEs ptr, filled on return.
  *
- * Description: returns 1 if valid,  0 on error.
+ * Description: returns 1 if valid,  0 on error, 2 if ignored header
  * If valid, returns pointers to PTEs.
  */
 static int is_gpt_valid(struct blk_desc *dev_desc, u64 lba,
@@ -965,6 +934,12 @@ static int is_gpt_valid(struct blk_desc *dev_desc, u64 lba,
 		return 0;
 	}
 
+	/* Invalid but nothing to yell about. */
+	if (le64_to_cpu(pgpt_head->signature) == GPT_HEADER_CHROMEOS_IGNORE) {
+		debug("ChromeOS 'IGNOREME' GPT header found and ignored\n");
+		return 2;
+	}
+
 	if (validate_gpt_header(pgpt_head, (lbaint_t)lba, dev_desc->lba))
 		return 0;
 
@@ -996,6 +971,40 @@ static int is_gpt_valid(struct blk_desc *dev_desc, u64 lba,
 	return 1;
 }
 
+/**
+ * find_valid_gpt() - finds a valid GPT header and PTEs
+ *
+ * gpt is a GPT header ptr, filled on return.
+ * ptes is a PTEs ptr, filled on return.
+ *
+ * Description: returns 1 if found a valid gpt,  0 on error.
+ * If valid, returns pointers to PTEs.
+ */
+static int find_valid_gpt(struct blk_desc *dev_desc, gpt_header *gpt_head,
+			  gpt_entry **pgpt_pte)
+{
+	int r;
+
+	r = is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA, gpt_head,
+			 pgpt_pte);
+
+	if (r != 1) {
+		if (r != 2)
+			printf("%s: *** ERROR: Invalid GPT ***\n", __func__);
+
+		if (is_gpt_valid(dev_desc, (dev_desc->lba - 1), gpt_head,
+				 pgpt_pte) != 1) {
+			printf("%s: *** ERROR: Invalid Backup GPT ***\n",
+			       __func__);
+			return 0;
+		}
+		if (r != 2)
+			printf("%s: ***        Using Backup GPT ***\n",
+			       __func__);
+	}
+	return 1;
+}
+
 /**
  * alloc_read_gpt_entries(): reads partition entries from disk
  * @dev_desc

+ 1 - 2
doc/README.rockchip

@@ -28,10 +28,9 @@ You will need:
 Building
 ========
 
-At present 12 RK3288 boards are supported:
+At present 11 RK3288 boards are supported:
 
    - EVB RK3288 - use evb-rk3288 configuration
-   - Fennec RK3288 - use fennec-rk3288 configuration
    - Firefly RK3288 - use firefly-rk3288 configuration
    - Hisense Chromebook - use chromebook_jerry configuration
    - Asus C100P Chromebook - use chromebook_minnie configuration

+ 12 - 0
drivers/clk/rockchip/clk_rk3328.c

@@ -745,10 +745,22 @@ static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent)
 	return -ENOENT;
 }
 
+static int rk3328_clk_enable(struct clk *clk)
+{
+	switch (clk->id) {
+	case HCLK_HOST0:
+		/* Required to successfully probe the ehci generic driver */
+		return 0;
+	}
+
+	return -ENOENT;
+}
+
 static struct clk_ops rk3328_clk_ops = {
 	.get_rate = rk3328_clk_get_rate,
 	.set_rate = rk3328_clk_set_rate,
 	.set_parent = rk3328_clk_set_parent,
+	.enable = rk3328_clk_enable,
 };
 
 static int rk3328_clk_probe(struct udevice *dev)

+ 81 - 78
drivers/ram/rockchip/sdram_rk3399.c

@@ -1488,6 +1488,84 @@ static void dram_all_config(struct dram_info *dram,
 	clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3);
 }
 
+static void set_cap_relate_config(const struct chan_info *chan,
+				  struct rk3399_sdram_params *params,
+				  unsigned int channel)
+{
+	u32 *denali_ctl = chan->pctl->denali_ctl;
+	u32 tmp;
+	struct rk3399_msch_timings *noc_timing;
+
+	if (params->base.dramtype == LPDDR3) {
+		tmp = (8 << params->ch[channel].cap_info.bw) /
+			(8 << params->ch[channel].cap_info.dbw);
+
+		/**
+		 * memdata_ratio
+		 * 1 -> 0, 2 -> 1, 4 -> 2
+		 */
+		clrsetbits_le32(&denali_ctl[197], 0x7,
+				(tmp >> 1));
+		clrsetbits_le32(&denali_ctl[198], 0x7 << 8,
+				(tmp >> 1) << 8);
+	}
+
+	noc_timing = &params->ch[channel].noc_timings;
+
+	/*
+	 * noc timing bw relate timing is 32 bit, and real bw is 16bit
+	 * actually noc reg is setting at function dram_all_config
+	 */
+	if (params->ch[channel].cap_info.bw == 16 &&
+	    noc_timing->ddrmode.b.mwrsize == 2) {
+		if (noc_timing->ddrmode.b.burstsize)
+			noc_timing->ddrmode.b.burstsize -= 1;
+		noc_timing->ddrmode.b.mwrsize -= 1;
+		noc_timing->ddrtimingc0.b.burstpenalty *= 2;
+		noc_timing->ddrtimingc0.b.wrtomwr *= 2;
+	}
+}
+
+static u32 calculate_ddrconfig(struct rk3399_sdram_params *params, u32 channel)
+{
+	unsigned int cs0_row = params->ch[channel].cap_info.cs0_row;
+	unsigned int col = params->ch[channel].cap_info.col;
+	unsigned int bw = params->ch[channel].cap_info.bw;
+	u16  ddr_cfg_2_rbc[] = {
+		/*
+		 * [6]	  highest bit col
+		 * [5:3]  max row(14+n)
+		 * [2]    insertion row
+		 * [1:0]  col(9+n),col, data bus 32bit
+		 *
+		 * highbitcol, max_row, insertion_row,  col
+		 */
+		((0 << 6) | (2 << 3) | (0 << 2) | 0), /* 0 */
+		((0 << 6) | (2 << 3) | (0 << 2) | 1), /* 1 */
+		((0 << 6) | (1 << 3) | (0 << 2) | 2), /* 2 */
+		((0 << 6) | (0 << 3) | (0 << 2) | 3), /* 3 */
+		((0 << 6) | (2 << 3) | (1 << 2) | 1), /* 4 */
+		((0 << 6) | (1 << 3) | (1 << 2) | 2), /* 5 */
+		((1 << 6) | (0 << 3) | (0 << 2) | 2), /* 6 */
+		((1 << 6) | (1 << 3) | (0 << 2) | 2), /* 7 */
+	};
+	u32 i;
+
+	col -= (bw == 2) ? 0 : 1;
+	col -= 9;
+
+	for (i = 0; i < 4; i++) {
+		if ((col == (ddr_cfg_2_rbc[i] & 0x3)) &&
+		    (cs0_row <= (((ddr_cfg_2_rbc[i] >> 3) & 0x7) + 14)))
+			break;
+	}
+
+	if (i >= 4)
+		i = -EINVAL;
+
+	return i;
+}
+
 #if !defined(CONFIG_RAM_RK3399_LPDDR4)
 static int default_data_training(struct dram_info *dram, u32 channel, u8 rank,
 				 struct rk3399_sdram_params *params)
@@ -1588,84 +1666,6 @@ static void set_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf, u32 stride)
 	rk_clrsetreg(&pmusgrf->soc_con4, 0x1f << 10, stride << 10);
 }
 
-static void set_cap_relate_config(const struct chan_info *chan,
-				  struct rk3399_sdram_params *params,
-				  unsigned int channel)
-{
-	u32 *denali_ctl = chan->pctl->denali_ctl;
-	u32 tmp;
-	struct rk3399_msch_timings *noc_timing;
-
-	if (params->base.dramtype == LPDDR3) {
-		tmp = (8 << params->ch[channel].cap_info.bw) /
-			(8 << params->ch[channel].cap_info.dbw);
-
-		/**
-		 * memdata_ratio
-		 * 1 -> 0, 2 -> 1, 4 -> 2
-		 */
-		clrsetbits_le32(&denali_ctl[197], 0x7,
-				(tmp >> 1));
-		clrsetbits_le32(&denali_ctl[198], 0x7 << 8,
-				(tmp >> 1) << 8);
-	}
-
-	noc_timing = &params->ch[channel].noc_timings;
-
-	/*
-	 * noc timing bw relate timing is 32 bit, and real bw is 16bit
-	 * actually noc reg is setting at function dram_all_config
-	 */
-	if (params->ch[channel].cap_info.bw == 16 &&
-	    noc_timing->ddrmode.b.mwrsize == 2) {
-		if (noc_timing->ddrmode.b.burstsize)
-			noc_timing->ddrmode.b.burstsize -= 1;
-		noc_timing->ddrmode.b.mwrsize -= 1;
-		noc_timing->ddrtimingc0.b.burstpenalty *= 2;
-		noc_timing->ddrtimingc0.b.wrtomwr *= 2;
-	}
-}
-
-static u32 calculate_ddrconfig(struct rk3399_sdram_params *params, u32 channel)
-{
-	unsigned int cs0_row = params->ch[channel].cap_info.cs0_row;
-	unsigned int col = params->ch[channel].cap_info.col;
-	unsigned int bw = params->ch[channel].cap_info.bw;
-	u16  ddr_cfg_2_rbc[] = {
-		/*
-		 * [6]	  highest bit col
-		 * [5:3]  max row(14+n)
-		 * [2]    insertion row
-		 * [1:0]  col(9+n),col, data bus 32bit
-		 *
-		 * highbitcol, max_row, insertion_row,  col
-		 */
-		((0 << 6) | (2 << 3) | (0 << 2) | 0), /* 0 */
-		((0 << 6) | (2 << 3) | (0 << 2) | 1), /* 1 */
-		((0 << 6) | (1 << 3) | (0 << 2) | 2), /* 2 */
-		((0 << 6) | (0 << 3) | (0 << 2) | 3), /* 3 */
-		((0 << 6) | (2 << 3) | (1 << 2) | 1), /* 4 */
-		((0 << 6) | (1 << 3) | (1 << 2) | 2), /* 5 */
-		((1 << 6) | (0 << 3) | (0 << 2) | 2), /* 6 */
-		((1 << 6) | (1 << 3) | (0 << 2) | 2), /* 7 */
-	};
-	u32 i;
-
-	col -= (bw == 2) ? 0 : 1;
-	col -= 9;
-
-	for (i = 0; i < 4; i++) {
-		if ((col == (ddr_cfg_2_rbc[i] & 0x3)) &&
-		    (cs0_row <= (((ddr_cfg_2_rbc[i] >> 3) & 0x7) + 14)))
-			break;
-	}
-
-	if (i >= 4)
-		i = -EINVAL;
-
-	return i;
-}
-
 /**
  * read mr_num mode register
  * rank = 1: cs0
@@ -2592,8 +2592,11 @@ static int sdram_init(struct dram_info *dram,
 		}
 
 		sdram_print_ddr_info(cap_info, &params->base);
+		set_memory_map(chan, channel, params);
+		cap_info->ddrconfig = calculate_ddrconfig(params, channel);
 
 		set_ddrconfig(chan, params, channel, cap_info->ddrconfig);
+		set_cap_relate_config(chan, params, channel);
 	}
 
 	if (params->base.num_channels == 0) {

+ 1 - 1
include/configs/evb_rk3399.h

@@ -8,7 +8,7 @@
 
 #include <configs/rk3399_common.h>
 
-#define CONFIG_SYS_MMC_ENV_DEV 1
+#define CONFIG_SYS_MMC_ENV_DEV 0
 
 #define SDRAM_BANK_SIZE			(2UL << 30)
 

+ 0 - 14
include/configs/fennec_rk3288.h

@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define ROCKCHIP_DEVICE_SETTINGS
-#include <configs/rk3288_common.h>
-
-#define CONFIG_SYS_MMC_ENV_DEV 0
-
-#endif

+ 0 - 1
include/configs/rk3036_common.h

@@ -8,7 +8,6 @@
 #include <asm/arch-rockchip/hardware.h>
 #include "rockchip-common.h"
 
-#define CONFIG_SYS_MALLOC_LEN		(32 << 20)
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
 

+ 0 - 1
include/configs/rk3128_common.h

@@ -10,7 +10,6 @@
 
 #define CONFIG_SYS_MAXARGS		16
 #define CONFIG_BAUDRATE			115200
-#define CONFIG_SYS_MALLOC_LEN		(32 << 20)
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
 

+ 0 - 1
include/configs/rk3188_common.h

@@ -12,7 +12,6 @@
 #include "rockchip-common.h"
 
 #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
-#define CONFIG_SYS_MALLOC_LEN		(32 << 20)
 #define CONFIG_SYS_CBSIZE		1024
 
 #ifdef CONFIG_SPL_ROCKCHIP_BACK_TO_BROM

+ 0 - 1
include/configs/rk322x_common.h

@@ -9,7 +9,6 @@
 #include "rockchip-common.h"
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SYS_MALLOC_LEN		(32 << 20)
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/*  64M */
 

+ 0 - 1
include/configs/rk3288_common.h

@@ -12,7 +12,6 @@
 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* 16MB */
 
 #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY
-#define CONFIG_SYS_MALLOC_LEN		(32 << 20)
 #define CONFIG_SYS_CBSIZE		1024
 
 #define CONFIG_ROCKCHIP_STIMER_BASE	0xff810020

+ 0 - 1
include/configs/rk3328_common.h

@@ -12,7 +12,6 @@
 
 #define CONFIG_ROCKCHIP_STIMER_BASE    0xff1d0020
 
-#define CONFIG_SYS_MALLOC_LEN		(32 << 20)
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
 

+ 0 - 1
include/configs/rk3368_common.h

@@ -16,7 +16,6 @@
 #define CONFIG_SYS_SDRAM_BASE		0
 #define SDRAM_MAX_SIZE			0xff000000
 #define CONFIG_BAUDRATE			115200
-#define CONFIG_SYS_MALLOC_LEN		(32 << 20)
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
 

+ 0 - 1
include/configs/rk3399_common.h

@@ -8,7 +8,6 @@
 
 #include "rockchip-common.h"
 
-#define CONFIG_SYS_MALLOC_LEN		(32 << 20)
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
 

+ 0 - 1
include/configs/rv1108_common.h

@@ -10,7 +10,6 @@
 
 #define CONFIG_IRAM_BASE		0x10080000
 
-#define CONFIG_SYS_MALLOC_LEN		(32 << 20)
 #define CONFIG_SYS_CBSIZE		1024
 #define CONFIG_SKIP_LOWLEVEL_INIT
 

+ 2 - 0
include/part_efi.h

@@ -25,6 +25,8 @@
 #define EFI_PMBR_OSTYPE_EFI_GPT 0xEE
 
 #define GPT_HEADER_SIGNATURE_UBOOT 0x5452415020494645ULL
+#define GPT_HEADER_CHROMEOS_IGNORE 0x454d45524f4e4749ULL // 'IGNOREME'
+
 #define GPT_HEADER_REVISION_V1 0x00010000
 #define GPT_PRIMARY_PARTITION_TABLE_LBA 1ULL
 #define GPT_ENTRY_NUMBERS		CONFIG_EFI_PARTITION_ENTRIES_NUMBERS