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@@ -460,13 +460,6 @@ void enable_basic_clocks(void)
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(*prcm)->cm_l4per_gpio6_clkctrl,
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(*prcm)->cm_l4per_gpio7_clkctrl,
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(*prcm)->cm_l4per_gpio8_clkctrl,
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-#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
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- (*prcm)->cm_l3init_ocp2scp1_clkctrl,
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- (*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
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-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
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- (*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
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-#endif
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-#endif
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0
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};
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@@ -498,29 +491,6 @@ void enable_basic_clocks(void)
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setbits_le32((*prcm)->cm_l3init_hsmmc2_clkctrl,
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HSMMC_CLKCTRL_CLKSEL_MASK);
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-#if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_OMAP)
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- /* Enable 960 MHz clock for dwc3 */
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- setbits_le32((*prcm)->cm_l3init_usb_otg_ss1_clkctrl,
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- OPTFCLKEN_REFCLK960M);
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-
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- /* Enable 32 KHz clock for dwc3 */
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- setbits_le32((*prcm)->cm_coreaon_usb_phy1_core_clkctrl,
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- USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
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-#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
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- /* Enable 960 MHz clock for dwc3 */
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- setbits_le32((*prcm)->cm_l3init_usb_otg_ss2_clkctrl,
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- OPTFCLKEN_REFCLK960M);
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-
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- /* Enable 32 KHz clock for dwc3 */
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- setbits_le32((*prcm)->cm_coreaon_usb_phy2_core_clkctrl,
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- USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K);
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-
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- /* Enable 60 MHz clock for USB2PHY2 */
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- setbits_le32((*prcm)->cm_coreaon_l3init_60m_gfclk_clkctrl,
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- L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK);
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-#endif
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-#endif
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-
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/* Set the correct clock dividers for mmc */
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setbits_le32((*prcm)->cm_l3init_hsmmc1_clkctrl,
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HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
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