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@@ -36,18 +36,18 @@
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#ifdef CONFIG_MTD_RAW_NAND
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#ifdef CONFIG_NXP_ESBC
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-#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
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-#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
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-#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
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+#define CFG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
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+#define CFG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
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+#define CFG_SYS_NAND_U_BOOT_START 0x00200000
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#else
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#ifdef CONFIG_TPL_BUILD
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-#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
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-#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
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-#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
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+#define CFG_SYS_NAND_U_BOOT_SIZE (576 << 10)
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+#define CFG_SYS_NAND_U_BOOT_DST (0x11000000)
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+#define CFG_SYS_NAND_U_BOOT_START (0x11000000)
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#elif defined(CONFIG_SPL_BUILD)
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-#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
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-#define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000
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-#define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000
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+#define CFG_SYS_NAND_U_BOOT_SIZE (128 << 10)
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+#define CFG_SYS_NAND_U_BOOT_DST 0xD0000000
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+#define CFG_SYS_NAND_U_BOOT_START 0xD0000000
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#endif
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#endif
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#endif
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@@ -167,23 +167,23 @@ extern unsigned long get_sdram_size(void);
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/* CFI for NOR Flash */
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/* NAND Flash on IFC */
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-#define CONFIG_SYS_NAND_BASE 0xff800000
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+#define CFG_SYS_NAND_BASE 0xff800000
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#ifdef CONFIG_PHYS_64BIT
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-#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
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+#define CFG_SYS_NAND_BASE_PHYS 0xfff800000ull
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#else
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-#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
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+#define CFG_SYS_NAND_BASE_PHYS CFG_SYS_NAND_BASE
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#endif
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#define CONFIG_MTD_PARTITION
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-#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
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+#define CFG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CFG_SYS_NAND_BASE_PHYS) \
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| CSPR_PORT_SIZE_8 \
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| CSPR_MSEL_NAND \
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| CSPR_V)
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-#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
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+#define CFG_SYS_NAND_AMASK IFC_AMASK(64*1024)
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#if defined(CONFIG_TARGET_P1010RDB_PA)
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-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
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+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
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| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
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| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
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| CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \
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@@ -192,7 +192,7 @@ extern unsigned long get_sdram_size(void);
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| CSOR_NAND_PB(32)) /* 32 Pages Per Block */
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#elif defined(CONFIG_TARGET_P1010RDB_PB)
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-#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
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+#define CFG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
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| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
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| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
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| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
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@@ -201,49 +201,49 @@ extern unsigned long get_sdram_size(void);
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| CSOR_NAND_PB(128)) /*Pages Per Block = 128 */
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#endif
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-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
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+#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
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#if defined(CONFIG_TARGET_P1010RDB_PA)
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/* NAND Flash Timing Params */
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-#define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
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+#define CFG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \
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FTIM0_NAND_TWP(0x0C) | \
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FTIM0_NAND_TWCHT(0x04) | \
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FTIM0_NAND_TWH(0x05)
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-#define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
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+#define CFG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \
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FTIM1_NAND_TWBE(0x1d) | \
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FTIM1_NAND_TRR(0x07) | \
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FTIM1_NAND_TRP(0x0c)
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-#define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
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+#define CFG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \
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FTIM2_NAND_TREH(0x05) | \
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FTIM2_NAND_TWHRE(0x0f)
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-#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
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+#define CFG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
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#elif defined(CONFIG_TARGET_P1010RDB_PB)
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/* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */
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/* ONFI NAND Flash mode0 Timing Params */
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-#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
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+#define CFG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \
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FTIM0_NAND_TWP(0x18) | \
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FTIM0_NAND_TWCHT(0x07) | \
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FTIM0_NAND_TWH(0x0a))
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-#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
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+#define CFG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \
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FTIM1_NAND_TWBE(0x39) | \
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FTIM1_NAND_TRR(0x0e) | \
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FTIM1_NAND_TRP(0x18))
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-#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
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+#define CFG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
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FTIM2_NAND_TREH(0x0a) | \
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FTIM2_NAND_TWHRE(0x1e))
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-#define CONFIG_SYS_NAND_FTIM3 0x0
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+#define CFG_SYS_NAND_FTIM3 0x0
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#endif
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/* Set up IFC registers for boot location NOR/NAND */
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#if defined(CONFIG_MTD_RAW_NAND) || defined(CONFIG_NAND_SECBOOT)
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-#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
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-#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
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-#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
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-#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
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-#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
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-#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
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-#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
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+#define CONFIG_SYS_CSPR0 CFG_SYS_NAND_CSPR
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+#define CONFIG_SYS_AMASK0 CFG_SYS_NAND_AMASK
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+#define CONFIG_SYS_CSOR0 CFG_SYS_NAND_CSOR
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+#define CONFIG_SYS_CS0_FTIM0 CFG_SYS_NAND_FTIM0
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+#define CONFIG_SYS_CS0_FTIM1 CFG_SYS_NAND_FTIM1
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+#define CONFIG_SYS_CS0_FTIM2 CFG_SYS_NAND_FTIM2
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+#define CONFIG_SYS_CS0_FTIM3 CFG_SYS_NAND_FTIM3
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#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
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#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
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@@ -259,13 +259,13 @@ extern unsigned long get_sdram_size(void);
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
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-#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
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-#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
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-#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
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-#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
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-#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
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-#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
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-#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
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+#define CONFIG_SYS_CSPR1 CFG_SYS_NAND_CSPR
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+#define CONFIG_SYS_AMASK1 CFG_SYS_NAND_AMASK
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+#define CONFIG_SYS_CSOR1 CFG_SYS_NAND_CSOR
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+#define CONFIG_SYS_CS1_FTIM0 CFG_SYS_NAND_FTIM0
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+#define CONFIG_SYS_CS1_FTIM1 CFG_SYS_NAND_FTIM1
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+#define CONFIG_SYS_CS1_FTIM2 CFG_SYS_NAND_FTIM2
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+#define CONFIG_SYS_CS1_FTIM3 CFG_SYS_NAND_FTIM3
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#endif
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/* CPLD on IFC */
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