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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Copyright (C) 2019 Marvell International Ltd.
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+ * Copyright (C) 2021 Stefan Roese <sr@denx.de>
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+ */
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+
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+#include <dm.h>
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+#include <dm/uclass.h>
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+#include <errno.h>
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+#include <input.h>
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+#include <iomux.h>
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+#include <log.h>
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+#include <serial.h>
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+#include <stdio_dev.h>
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+#include <string.h>
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+#include <watchdog.h>
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+#include <linux/delay.h>
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+#include <asm/io.h>
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+#include <mach/cvmx-regs.h>
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+#include <mach/cvmx-bootmem.h>
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+
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+#define DRIVER_NAME "pci-console"
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+#define OCTEONTX_PCIE_CONSOLE_NAME_LEN 16
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+
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+/* Current versions */
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+#define OCTEON_PCIE_CONSOLE_MAJOR_VERSION 1
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+#define OCTEON_PCIE_CONSOLE_MINOR_VERSION 0
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+
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+#define OCTEON_PCIE_CONSOLE_BLOCK_NAME "__pci_console"
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+
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+/*
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+ * Structure that defines a single console.
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+ * Note: when read_index == write_index, the buffer is empty.
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+ * The actual usable size of each console is console_buf_size -1;
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+ */
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+struct octeon_pcie_console {
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+ u64 input_base_addr;
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+ u32 input_read_index;
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+ u32 input_write_index;
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+ u64 output_base_addr;
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+ u32 output_read_index;
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+ u32 output_write_index;
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+ u32 lock;
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+ u32 buf_size;
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+};
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+
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+/*
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+ * This is the main container structure that contains all the information
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+ * about all PCI consoles. The address of this structure is passed to various
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+ * routines that operation on PCI consoles.
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+ */
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+struct octeon_pcie_console_desc {
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+ u32 major_version;
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+ u32 minor_version;
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+ u32 lock;
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+ u32 flags;
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+ u32 num_consoles;
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+ u32 pad;
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+ /* must be 64 bit aligned here... */
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+ /* Array of addresses of octeon_pcie_console_t structures */
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+ u64 console_addr_array[0];
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+ /* Implicit storage for console_addr_array */
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+};
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+
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+struct octeon_pcie_console_priv {
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+ struct octeon_pcie_console *console;
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+ int console_num;
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+ bool console_active;
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+};
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+
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+/* Flag definitions for read/write functions */
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+enum {
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+ /*
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+ * If set, read/write functions won't block waiting for space or data.
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+ * For reads, 0 bytes may be read, and for writes not all of the
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+ * supplied data may be written.
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+ */
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+ OCT_PCI_CON_FLAG_NONBLOCK = 1 << 0,
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+};
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+
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+static int buffer_free_bytes(u32 buffer_size, u32 wr_idx, u32 rd_idx)
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+{
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+ if (rd_idx >= buffer_size || wr_idx >= buffer_size)
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+ return -1;
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+
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+ return ((buffer_size - 1) - (wr_idx - rd_idx)) % buffer_size;
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+}
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+
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+static int buffer_avail_bytes(u32 buffer_size, u32 wr_idx, u32 rd_idx)
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+{
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+ if (rd_idx >= buffer_size || wr_idx >= buffer_size)
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+ return -1;
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+
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+ return buffer_size - 1 - buffer_free_bytes(buffer_size, wr_idx, rd_idx);
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+}
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+
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+static int buffer_read_avail(struct udevice *dev, unsigned int console_num)
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+{
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+ struct octeon_pcie_console_priv *priv = dev_get_priv(dev);
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+ struct octeon_pcie_console *cons_ptr = priv->console;
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+ int avail;
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+
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+ avail = buffer_avail_bytes(cons_ptr->buf_size,
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+ cons_ptr->input_write_index,
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+ cons_ptr->input_read_index);
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+ if (avail >= 0)
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+ return avail;
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+
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+ return 0;
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+}
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+
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+static int octeon_pcie_console_read(struct udevice *dev,
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+ unsigned int console_num, char *buffer,
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+ int buffer_size, u32 flags)
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+{
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+ struct octeon_pcie_console_priv *priv = dev_get_priv(dev);
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+ struct octeon_pcie_console *cons_ptr = priv->console;
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+ int avail;
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+ char *buf_ptr;
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+ int bytes_read;
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+ int read_size;
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+
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+ buf_ptr = (char *)cvmx_phys_to_ptr(cons_ptr->input_base_addr);
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+
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+ avail = buffer_avail_bytes(cons_ptr->buf_size,
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+ cons_ptr->input_write_index,
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+ cons_ptr->input_read_index);
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+ if (avail < 0)
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+ return avail;
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+
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+ if (!(flags & OCT_PCI_CON_FLAG_NONBLOCK)) {
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+ /* Wait for some data to be available */
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+ while (0 == (avail = buffer_avail_bytes(cons_ptr->buf_size,
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+ cons_ptr->input_write_index,
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+ cons_ptr->input_read_index))) {
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+ mdelay(10);
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+ WATCHDOG_RESET();
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+ }
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+ }
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+
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+ bytes_read = 0;
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+
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+ /* Don't overflow the buffer passed to us */
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+ read_size = min_t(int, avail, buffer_size);
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+
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+ /* Limit ourselves to what we can input in a contiguous block */
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+ if (cons_ptr->input_read_index + read_size >= cons_ptr->buf_size)
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+ read_size = cons_ptr->buf_size - cons_ptr->input_read_index;
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+
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+ memcpy(buffer, buf_ptr + cons_ptr->input_read_index, read_size);
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+ cons_ptr->input_read_index =
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+ (cons_ptr->input_read_index + read_size) % cons_ptr->buf_size;
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+ bytes_read += read_size;
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+
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+ /* Mark the PCIe console to be active from now on */
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+ if (bytes_read)
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+ priv->console_active = true;
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+
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+ return bytes_read;
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+}
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+
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+static int octeon_pcie_console_write(struct udevice *dev,
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+ unsigned int console_num,
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+ const char *buffer,
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+ int bytes_to_write, u32 flags)
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+{
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+ struct octeon_pcie_console_priv *priv = dev_get_priv(dev);
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+ struct octeon_pcie_console *cons_ptr = priv->console;
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+ int avail;
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+ char *buf_ptr;
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+ int bytes_written;
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+
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+ buf_ptr = (char *)cvmx_phys_to_ptr(cons_ptr->output_base_addr);
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+ bytes_written = 0;
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+ while (bytes_to_write > 0) {
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+ avail = buffer_free_bytes(cons_ptr->buf_size,
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+ cons_ptr->output_write_index,
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+ cons_ptr->output_read_index);
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+
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+ if (avail > 0) {
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+ int write_size = min_t(int, avail, bytes_to_write);
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+
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+ /*
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+ * Limit ourselves to what we can output in a contiguous
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+ * block
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+ */
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+ if (cons_ptr->output_write_index + write_size >=
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+ cons_ptr->buf_size) {
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+ write_size = cons_ptr->buf_size -
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+ cons_ptr->output_write_index;
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+ }
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+
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+ memcpy(buf_ptr + cons_ptr->output_write_index,
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+ buffer + bytes_written, write_size);
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+ /*
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+ * Make sure data is visible before changing write
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+ * index
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+ */
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+ CVMX_SYNCW;
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+ cons_ptr->output_write_index =
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+ (cons_ptr->output_write_index + write_size) %
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+ cons_ptr->buf_size;
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+ bytes_to_write -= write_size;
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+ bytes_written += write_size;
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+ } else if (avail == 0) {
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+ /*
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+ * Check to see if we should wait for room, or return
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+ * after a partial write
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+ */
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+ if (flags & OCT_PCI_CON_FLAG_NONBLOCK)
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+ goto done;
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+
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+ WATCHDOG_RESET();
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+ mdelay(10); /* Delay if we are spinning */
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+ } else {
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+ bytes_written = -1;
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+ goto done;
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+ }
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+ }
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+
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+done:
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+ return bytes_written;
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+}
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+
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+static struct octeon_pcie_console_desc *octeon_pcie_console_init(int num_consoles,
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+ int buffer_size)
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+{
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+ struct octeon_pcie_console_desc *cons_desc_ptr;
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+ struct octeon_pcie_console *cons_ptr;
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+ s64 addr;
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+ u64 avail_addr;
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+ int alloc_size;
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+ int i;
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+
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+ /* Compute size required for pci console structure */
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+ alloc_size = num_consoles *
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+ (buffer_size * 2 + sizeof(struct octeon_pcie_console) +
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+ sizeof(u64)) + sizeof(struct octeon_pcie_console_desc);
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+
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+ /*
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+ * Allocate memory for the consoles. This must be in the range
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+ * addresssible by the bootloader.
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+ * Try to do so in a manner which minimizes fragmentation. We try to
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+ * put it at the top of DDR0 or bottom of DDR2 first, and only do
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+ * generic allocation if those fail
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+ */
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+ addr = cvmx_bootmem_phy_named_block_alloc(alloc_size,
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+ OCTEON_DDR0_SIZE - alloc_size - 128,
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+ OCTEON_DDR0_SIZE, 128,
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+ OCTEON_PCIE_CONSOLE_BLOCK_NAME,
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+ CVMX_BOOTMEM_FLAG_END_ALLOC);
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+ if (addr < 0) {
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+ addr = cvmx_bootmem_phy_named_block_alloc(alloc_size, 0,
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+ 0x1fffffff, 128,
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+ OCTEON_PCIE_CONSOLE_BLOCK_NAME,
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+ CVMX_BOOTMEM_FLAG_END_ALLOC);
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+ }
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+ if (addr < 0)
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+ return 0;
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+
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+ cons_desc_ptr = cvmx_phys_to_ptr(addr);
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+
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+ /* Clear entire alloc'ed memory */
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+ memset(cons_desc_ptr, 0, alloc_size);
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+
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+ /* Initialize as locked until we are done */
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+ cons_desc_ptr->lock = 1;
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+ CVMX_SYNCW;
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+ cons_desc_ptr->num_consoles = num_consoles;
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+ cons_desc_ptr->flags = 0;
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+ cons_desc_ptr->major_version = OCTEON_PCIE_CONSOLE_MAJOR_VERSION;
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+ cons_desc_ptr->minor_version = OCTEON_PCIE_CONSOLE_MINOR_VERSION;
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+
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+ avail_addr = addr + sizeof(struct octeon_pcie_console_desc) +
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+ num_consoles * sizeof(u64);
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+
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+ for (i = 0; i < num_consoles; i++) {
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+ cons_desc_ptr->console_addr_array[i] = avail_addr;
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+ cons_ptr = (void *)cons_desc_ptr->console_addr_array[i];
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+ avail_addr += sizeof(struct octeon_pcie_console);
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+ cons_ptr->input_base_addr = avail_addr;
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+ avail_addr += buffer_size;
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+ cons_ptr->output_base_addr = avail_addr;
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+ avail_addr += buffer_size;
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+ cons_ptr->buf_size = buffer_size;
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+ }
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+ CVMX_SYNCW;
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+ cons_desc_ptr->lock = 0;
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+
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+ return cvmx_phys_to_ptr(addr);
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+}
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+
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+static int octeon_pcie_console_getc(struct udevice *dev)
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+{
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+ char c;
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+
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+ octeon_pcie_console_read(dev, 0, &c, 1, 0);
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+ return c;
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+}
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+
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+static int octeon_pcie_console_putc(struct udevice *dev, const char c)
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+{
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+ struct octeon_pcie_console_priv *priv = dev_get_priv(dev);
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+
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+ if (priv->console_active)
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+ octeon_pcie_console_write(dev, 0, (char *)&c, 1, 0);
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+
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+ return 0;
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+}
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+
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+static int octeon_pcie_console_pending(struct udevice *dev, bool input)
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+{
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+ if (input) {
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+ udelay(100);
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+ return buffer_read_avail(dev, 0) > 0;
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+ }
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+
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+ return 0;
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+}
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+
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+static const struct dm_serial_ops octeon_pcie_console_ops = {
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+ .getc = octeon_pcie_console_getc,
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+ .putc = octeon_pcie_console_putc,
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+ .pending = octeon_pcie_console_pending,
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+};
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+
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+static int octeon_pcie_console_probe(struct udevice *dev)
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+{
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+ struct octeon_pcie_console_priv *priv = dev_get_priv(dev);
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+ struct octeon_pcie_console_desc *cons_desc;
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+ int console_count;
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+ int console_size;
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+ int console_num;
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+
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+ /*
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+ * Currently only 1 console is supported. Perhaps we need to add
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+ * a console nexus if more than one needs to be supported.
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+ */
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+ console_count = 1;
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+ console_size = 1024;
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+ console_num = 0;
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+
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+ cons_desc = octeon_pcie_console_init(console_count, console_size);
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+ priv->console =
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+ cvmx_phys_to_ptr(cons_desc->console_addr_array[console_num]);
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+
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+ debug("PCI console init succeeded, %d consoles, %d bytes each\n",
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+ console_count, console_size);
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+
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+ return 0;
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+}
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+
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+static const struct udevice_id octeon_pcie_console_serial_id[] = {
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+ { .compatible = "marvell,pci-console", },
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+ { },
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+};
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+
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+U_BOOT_DRIVER(octeon_pcie_console) = {
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+ .name = DRIVER_NAME,
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+ .id = UCLASS_SERIAL,
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+ .ops = &octeon_pcie_console_ops,
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+ .of_match = of_match_ptr(octeon_pcie_console_serial_id),
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+ .probe = octeon_pcie_console_probe,
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+ .priv_auto = sizeof(struct octeon_pcie_console_priv),
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+};
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