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@@ -10,6 +10,7 @@
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#include <asm/gpio.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm/mach-imx/boot_mode.h>
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+#include <fsl_esdhc.h>
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#include <linux/libfdt.h>
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#include <spl.h>
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@@ -141,4 +142,37 @@ void board_init_f(ulong dummy)
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void reset_cpu(ulong addr)
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{
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}
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+
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+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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+ PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
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+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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+
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+static iomux_v3_cfg_t const usdhc1_pads[] = {
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+ MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_NAND_READY_B__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_NAND_CE0_B__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_NAND_CE1_B__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+ MX6_PAD_NAND_CLE__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
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+};
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+
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+static struct fsl_esdhc_cfg usdhc_cfg[1] = {
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+ {USDHC1_BASE_ADDR},
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+};
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+
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+int board_mmc_getcd(struct mmc *mmc)
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+{
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+ return 1;
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+}
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+
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+int board_mmc_init(bd_t *bis)
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+{
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+ imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
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+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
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+}
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#endif
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