瀏覽代碼

riscv: dts: jh7110: Add a new clock input to gmac

To be compatible with the VisionFive 2 board.
The code is ported from tag JH7110_VF2_515_v3.9.3 of VF2 repo.

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Hal Feng 9 月之前
父節點
當前提交
4b07186e8e
共有 1 個文件被更改,包括 8 次插入4 次删除
  1. 8 4
      arch/riscv/dts/jh7110.dtsi

+ 8 - 4
arch/riscv/dts/jh7110.dtsi

@@ -856,13 +856,15 @@
 				"ptp_ref",
 				"stmmaceth",
 				"pclk",
-				"gtxc";
+				"gtxc",
+				"rmii_rtx";
 			clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
 				 <&clkgen JH7110_U0_GMAC5_CLK_TX>,
 				 <&clkgen JH7110_GMAC0_PTP>,
 				 <&clkgen JH7110_U0_GMAC5_CLK_AHB>,
 				 <&clkgen JH7110_U0_GMAC5_CLK_AXI>,
-				 <&clkgen JH7110_GMAC0_GTXC>;
+				 <&clkgen JH7110_GMAC0_GTXC>,
+				 <&clkgen JH7110_GMAC0_RMII_RTX>;
 			resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
 				 <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
 			reset-names = "ahb", "stmmaceth";
@@ -897,13 +899,15 @@
 				"ptp_ref",
 				"stmmaceth",
 				"pclk",
-				"gtxc";
+				"gtxc",
+				"rmii_rtx";
 			clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
 				 <&clkgen JH7110_GMAC5_CLK_TX>,
 				 <&clkgen JH7110_GMAC5_CLK_PTP>,
 				 <&clkgen JH7110_GMAC5_CLK_AHB>,
 				 <&clkgen JH7110_GMAC5_CLK_AXI>,
-				 <&clkgen JH7110_GMAC1_GTXC>;
+				 <&clkgen JH7110_GMAC1_GTXC>,
+				 <&clkgen JH7110_GMAC1_RMII_RTX>;
 			resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
 				 <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
 			reset-names = "ahb", "stmmaceth";