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@@ -19,8 +19,6 @@
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/* The PHY is autodetected, so no MII PHY address is needed here */
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#define PHY_ANEG_TIMEOUT 8000
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-/* Environment */
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-
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/* Enable SPI NOR flash reset, needed for SPI booting */
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#define CONFIG_SPI_N25Q256A_RESET
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@@ -36,15 +34,6 @@
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#define CONFIG_ENV_OFFSET 0x000e0000
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
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-/*
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- * The QSPI NOR flash layout on SR1500:
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- *
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- * 0000.0000 - 0003.ffff: SPL (4 times)
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- * 0004.0000 - 000d.ffff: U-Boot
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- * 000e.0000 - 000e.ffff: env1
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- * 000f.0000 - 000f.ffff: env2
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- */
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-
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/* The rest of the configuration is shared */
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#include <configs/socfpga_common.h>
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