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@@ -1,258 +0,0 @@
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-/*
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- * (C) Copyright 2015
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- * Kamil Lulko, <kamil.lulko@gmail.com>
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- *
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- * (C) Copyright 2014
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- * STMicroelectronics
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- *
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- * SPDX-License-Identifier: GPL-2.0+
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- */
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-
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-#include <common.h>
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-#include <stm32_rcc.h>
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-#include <asm/io.h>
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-#include <asm/arch/stm32.h>
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-#include <asm/arch/stm32_periph.h>
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-
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-#define RCC_CR_HSION (1 << 0)
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-#define RCC_CR_HSEON (1 << 16)
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-#define RCC_CR_HSERDY (1 << 17)
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-#define RCC_CR_HSEBYP (1 << 18)
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-#define RCC_CR_CSSON (1 << 19)
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-#define RCC_CR_PLLON (1 << 24)
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-#define RCC_CR_PLLRDY (1 << 25)
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-
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-#define RCC_PLLCFGR_PLLM_MASK 0x3F
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-#define RCC_PLLCFGR_PLLN_MASK 0x7FC0
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-#define RCC_PLLCFGR_PLLP_MASK 0x30000
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-#define RCC_PLLCFGR_PLLQ_MASK 0xF000000
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-#define RCC_PLLCFGR_PLLSRC (1 << 22)
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-#define RCC_PLLCFGR_PLLN_SHIFT 6
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-#define RCC_PLLCFGR_PLLP_SHIFT 16
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-#define RCC_PLLCFGR_PLLQ_SHIFT 24
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-
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-#define RCC_CFGR_AHB_PSC_MASK 0xF0
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-#define RCC_CFGR_APB1_PSC_MASK 0x1C00
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-#define RCC_CFGR_APB2_PSC_MASK 0xE000
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-#define RCC_CFGR_SW0 (1 << 0)
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-#define RCC_CFGR_SW1 (1 << 1)
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-#define RCC_CFGR_SW_MASK 0x3
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-#define RCC_CFGR_SW_HSI 0
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-#define RCC_CFGR_SW_HSE RCC_CFGR_SW0
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-#define RCC_CFGR_SW_PLL RCC_CFGR_SW1
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-#define RCC_CFGR_SWS0 (1 << 2)
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-#define RCC_CFGR_SWS1 (1 << 3)
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-#define RCC_CFGR_SWS_MASK 0xC
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-#define RCC_CFGR_SWS_HSI 0
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-#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
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-#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
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-#define RCC_CFGR_HPRE_SHIFT 4
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-#define RCC_CFGR_PPRE1_SHIFT 10
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-#define RCC_CFGR_PPRE2_SHIFT 13
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-
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-#define RCC_APB1ENR_PWREN (1 << 28)
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-
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-/*
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- * RCC USART specific definitions
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- */
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-#define RCC_ENR_USART1EN (1 << 4)
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-#define RCC_ENR_USART2EN (1 << 17)
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-#define RCC_ENR_USART3EN (1 << 18)
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-#define RCC_ENR_USART6EN (1 << 5)
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-
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-#define PWR_CR_VOS0 (1 << 14)
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-#define PWR_CR_VOS1 (1 << 15)
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-#define PWR_CR_VOS_MASK 0xC000
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-#define PWR_CR_VOS_SCALE_MODE_1 (PWR_CR_VOS0 | PWR_CR_VOS1)
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-#define PWR_CR_VOS_SCALE_MODE_2 (PWR_CR_VOS1)
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-#define PWR_CR_VOS_SCALE_MODE_3 (PWR_CR_VOS0)
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-
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-/*
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- * RCC GPIO specific definitions
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- */
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-#define RCC_ENR_GPIO_A_EN (1 << 0)
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-#define RCC_ENR_GPIO_B_EN (1 << 1)
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-#define RCC_ENR_GPIO_C_EN (1 << 2)
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-#define RCC_ENR_GPIO_D_EN (1 << 3)
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-#define RCC_ENR_GPIO_E_EN (1 << 4)
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-#define RCC_ENR_GPIO_F_EN (1 << 5)
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-#define RCC_ENR_GPIO_G_EN (1 << 6)
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-#define RCC_ENR_GPIO_H_EN (1 << 7)
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-#define RCC_ENR_GPIO_I_EN (1 << 8)
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-#define RCC_ENR_GPIO_J_EN (1 << 9)
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-#define RCC_ENR_GPIO_K_EN (1 << 10)
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-
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-#if !defined(CONFIG_STM32_HSE_HZ)
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-#error "CONFIG_STM32_HSE_HZ not defined!"
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-#else
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-#if (CONFIG_STM32_HSE_HZ == 8000000)
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-#if (CONFIG_SYS_CLK_FREQ == 180000000)
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-/* 180 MHz */
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-struct pll_psc sys_pll_psc = {
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- .pll_m = 8,
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- .pll_n = 360,
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- .pll_p = 2,
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- .pll_q = 8,
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- .ahb_psc = AHB_PSC_1,
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- .apb1_psc = APB_PSC_4,
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- .apb2_psc = APB_PSC_2
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-};
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-#else
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-/* default 168 MHz */
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-struct pll_psc sys_pll_psc = {
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- .pll_m = 8,
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- .pll_n = 336,
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- .pll_p = 2,
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- .pll_q = 7,
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- .ahb_psc = AHB_PSC_1,
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- .apb1_psc = APB_PSC_4,
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- .apb2_psc = APB_PSC_2
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-};
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-#endif
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-#else
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-#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
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-#endif
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-#endif
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-
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-int configure_clocks(void)
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-{
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- /* Reset RCC configuration */
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- setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
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- writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
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- clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON
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- | RCC_CR_PLLON));
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- writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */
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- clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP);
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- writel(0, &STM32_RCC->cir); /* Disable all interrupts */
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-
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- /* Configure for HSE+PLL operation */
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- setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON);
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- while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
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- ;
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-
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- /* Enable high performance mode, System frequency up to 180 MHz */
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- setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
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- writel(PWR_CR_VOS_SCALE_MODE_1, &STM32_PWR->cr);
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-
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- setbits_le32(&STM32_RCC->cfgr, ((
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- sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
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- | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
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- | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
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-
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- writel(sys_pll_psc.pll_m
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- | (sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT)
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- | (((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT)
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- | (sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT),
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- &STM32_RCC->pllcfgr);
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- setbits_le32(&STM32_RCC->pllcfgr, RCC_PLLCFGR_PLLSRC);
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-
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- setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON);
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-
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- while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
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- ;
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-
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- stm32_flash_latency_cfg(5);
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- clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
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- setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
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-
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- while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) !=
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- RCC_CFGR_SWS_PLL)
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- ;
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-
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- return 0;
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-}
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-
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-unsigned long clock_get(enum clock clck)
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-{
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- u32 sysclk = 0;
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- u32 shift = 0;
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- /* Prescaler table lookups for clock computation */
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- u8 ahb_psc_table[16] = {
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- 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
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- };
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- u8 apb_psc_table[8] = {
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- 0, 0, 0, 0, 1, 2, 3, 4
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- };
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-
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- if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
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- RCC_CFGR_SWS_PLL) {
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- u16 pllm, plln, pllp;
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- pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
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- plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
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- >> RCC_PLLCFGR_PLLN_SHIFT);
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- pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
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- >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
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- sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
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- }
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-
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- switch (clck) {
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- case CLOCK_CORE:
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- return sysclk;
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- break;
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- case CLOCK_AHB:
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- shift = ahb_psc_table[(
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- (readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
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- >> RCC_CFGR_HPRE_SHIFT)];
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- return sysclk >>= shift;
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- break;
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- case CLOCK_APB1:
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- shift = apb_psc_table[(
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- (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
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- >> RCC_CFGR_PPRE1_SHIFT)];
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- return sysclk >>= shift;
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- break;
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- case CLOCK_APB2:
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- shift = apb_psc_table[(
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- (readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
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- >> RCC_CFGR_PPRE2_SHIFT)];
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- return sysclk >>= shift;
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- break;
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- default:
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- return 0;
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- break;
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- }
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-}
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-
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-void clock_setup(int peripheral)
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-{
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- switch (peripheral) {
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- case USART1_CLOCK_CFG:
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- setbits_le32(&STM32_RCC->apb2enr, RCC_ENR_USART1EN);
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- break;
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- case GPIO_A_CLOCK_CFG:
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- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_A_EN);
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- break;
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- case GPIO_B_CLOCK_CFG:
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- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_B_EN);
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- break;
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- case GPIO_C_CLOCK_CFG:
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- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_C_EN);
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- break;
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- case GPIO_D_CLOCK_CFG:
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- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_D_EN);
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- break;
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- case GPIO_E_CLOCK_CFG:
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- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_E_EN);
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- break;
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- case GPIO_F_CLOCK_CFG:
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- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_F_EN);
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- break;
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- case GPIO_G_CLOCK_CFG:
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- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_G_EN);
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- break;
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- case GPIO_H_CLOCK_CFG:
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- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_H_EN);
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- break;
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- case GPIO_I_CLOCK_CFG:
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- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_I_EN);
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- break;
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- case GPIO_J_CLOCK_CFG:
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- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_J_EN);
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- break;
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- case GPIO_K_CLOCK_CFG:
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- setbits_le32(&STM32_RCC->ahb1enr, RCC_ENR_GPIO_K_EN);
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- break;
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- default:
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- break;
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- }
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-}
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