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@@ -7,9 +7,13 @@
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#include <env.h>
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#include <errno.h>
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#include <init.h>
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+#include <miiphy.h>
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+#include <netdev.h>
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+#include <linux/delay.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm-generic/gpio.h>
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#include <asm/arch/imx8mp_pins.h>
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+#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/gpio.h>
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@@ -40,10 +44,69 @@ int board_early_init_f(void)
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return 0;
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}
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-int board_init(void)
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+static void setup_fec(void)
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+{
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+ struct iomuxc_gpr_base_regs *gpr =
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+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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+
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+ /* Enable RGMII TX clk output */
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+ setbits_le32(&gpr->gpr[1], BIT(22));
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+}
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+
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+#define EQOS_RST_PAD IMX_GPIO_NR(4, 22)
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+static iomux_v3_cfg_t const eqos_rst_pads[] = {
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+ MX8MP_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
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+};
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+
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+static void setup_iomux_eqos(void)
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{
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+ imx_iomux_v3_setup_multiple_pads(eqos_rst_pads,
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+ ARRAY_SIZE(eqos_rst_pads));
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+
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+ gpio_request(EQOS_RST_PAD, "eqos_rst");
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+ gpio_direction_output(EQOS_RST_PAD, 0);
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+ mdelay(15);
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+ gpio_direction_output(EQOS_RST_PAD, 1);
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+ mdelay(100);
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+}
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+
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+static int setup_eqos(void)
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+{
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+ struct iomuxc_gpr_base_regs *gpr =
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+ (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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+
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+ setup_iomux_eqos();
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+
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+ /* set INTF as RGMII, enable RGMII TXC clock */
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+ clrsetbits_le32(&gpr->gpr[1],
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+ IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
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+ setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
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+
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+ return set_clk_eqos(ENET_125MHZ);
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+}
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+
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+#if CONFIG_IS_ENABLED(NET)
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+int board_phy_config(struct phy_device *phydev)
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+{
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+ if (phydev->drv->config)
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+ phydev->drv->config(phydev);
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return 0;
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}
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+#endif
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+
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+int board_init(void)
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+{
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+ int ret = 0;
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+
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+ if (CONFIG_IS_ENABLED(FEC_MXC)) {
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+ setup_fec();
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+
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+ if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
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+ ret = setup_eqos();
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+ }
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+
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+ return ret;
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+}
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int board_late_init(void)
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{
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