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@@ -1317,6 +1317,19 @@ int exynos5_set_epll_clk(unsigned long rate)
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return 0;
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}
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+static int exynos5420_set_i2s_clk_source(void)
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+{
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+ struct exynos5420_clock *clk =
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+ (struct exynos5420_clock *)samsung_get_base_clock();
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+
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+ setbits_le32(&clk->src_top6, EXYNOS5420_CLK_SRC_MOUT_EPLL);
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+ clrsetbits_le32(&clk->src_mau, EXYNOS5420_AUDIO0_SEL_MASK,
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+ (EXYNOS5420_CLK_SRC_SCLK_EPLL));
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+ setbits_le32(EXYNOS5_AUDIOSS_BASE, 1 << 0);
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+
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+ return 0;
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+}
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+
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int exynos5_set_i2s_clk_source(unsigned int i2s_id)
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{
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struct exynos5_clock *clk =
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@@ -1758,8 +1771,12 @@ int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq,
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int set_i2s_clk_source(unsigned int i2s_id)
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{
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- if (cpu_is_exynos5())
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- return exynos5_set_i2s_clk_source(i2s_id);
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+ if (cpu_is_exynos5()) {
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+ if (proid_is_exynos542x())
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+ return exynos5420_set_i2s_clk_source();
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+ else
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+ return exynos5_set_i2s_clk_source(i2s_id);
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+ }
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return 0;
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}
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