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@@ -246,8 +246,15 @@ static struct clk *starfive_clk_composite(void __iomem *reg,
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goto fail;
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div->reg = reg + offset;
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- div->shift = STARFIVE_CLK_DIV_SHIFT;
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- div->width = div_width;
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+ if ((offset == SYS_OFFSET(JH7110_UART3_CLK_CORE)) ||
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+ (offset == SYS_OFFSET(JH7110_UART4_CLK_CORE)) ||
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+ (offset == SYS_OFFSET(JH7110_UART5_CLK_CORE))) {
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+ div->shift = 8;
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+ div->width = 8;
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+ } else {
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+ div->shift = STARFIVE_CLK_DIV_SHIFT;
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+ div->width = div_width;
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+ }
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div->flags = CLK_DIVIDER_ONE_BASED;
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div->table = NULL;
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}
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@@ -321,11 +328,11 @@ static int jh7110_clk_init(struct udevice *dev)
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clk_dm(JH7110_CPU_CORE,
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starfive_clk_divider(priv->sys,
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"cpu_core", "cpu_root",
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- SYS_OFFSET(JH7110_CPU_CORE), 3));
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+ SYS_OFFSET(JH7110_CPU_CORE), 3));
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clk_dm(JH7110_CPU_BUS,
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starfive_clk_divider(priv->sys,
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"cpu_bus", "cpu_core",
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- SYS_OFFSET(JH7110_CPU_BUS), 2));
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+ SYS_OFFSET(JH7110_CPU_BUS), 2));
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clk_dm(JH7110_DDR_ROOT,
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starfive_clk_fix_factor(priv->sys,
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"ddr_root", "pll1_out", 1, 1));
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@@ -333,9 +340,10 @@ static int jh7110_clk_init(struct udevice *dev)
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starfive_clk_fix_factor(priv->sys,
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"gmacusb_root", "pll0_out", 1, 1));
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clk_dm(JH7110_PERH_ROOT,
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- starfive_clk_mux(priv->sys, "perh_root",
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- SYS_OFFSET(JH7110_PERH_ROOT), 1,
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- perh_root_sels, ARRAY_SIZE(perh_root_sels)));
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+ starfive_clk_composite(priv->sys,
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+ "perh_root",
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+ perh_root_sels, ARRAY_SIZE(perh_root_sels),
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+ SYS_OFFSET(JH7110_PERH_ROOT), 1, 0, 2));
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clk_dm(JH7110_BUS_ROOT,
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starfive_clk_mux(priv->sys, "bus_root",
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@@ -517,9 +525,9 @@ static int jh7110_clk_init(struct udevice *dev)
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"u3_dw_uart_clk_apb", "apb0",
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SYS_OFFSET(JH7110_UART3_CLK_APB)));
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clk_dm(JH7110_UART3_CLK_CORE,
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- starfive_clk_gate(priv->sys,
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- "u3_dw_uart_clk_core", "perh_root",
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- SYS_OFFSET(JH7110_UART3_CLK_CORE)));
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+ starfive_clk_gate_divider(priv->sys,
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+ "u3_dw_uart_clk_core", "perh_root",
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+ SYS_OFFSET(JH7110_UART3_CLK_CORE), 8));
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/*UART4*/
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clk_dm(JH7110_UART4_CLK_APB,
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@@ -527,9 +535,9 @@ static int jh7110_clk_init(struct udevice *dev)
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"u4_dw_uart_clk_apb", "apb0",
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SYS_OFFSET(JH7110_UART4_CLK_APB)));
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clk_dm(JH7110_UART4_CLK_CORE,
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- starfive_clk_gate(priv->sys,
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- "u4_dw_uart_clk_core", "perh_root",
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- SYS_OFFSET(JH7110_UART4_CLK_CORE)));
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+ starfive_clk_gate_divider(priv->sys,
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+ "u4_dw_uart_clk_core", "perh_root",
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+ SYS_OFFSET(JH7110_UART4_CLK_CORE), 8));
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/*UART5*/
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clk_dm(JH7110_UART5_CLK_APB,
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@@ -537,9 +545,9 @@ static int jh7110_clk_init(struct udevice *dev)
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"u5_dw_uart_clk_apb", "apb0",
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SYS_OFFSET(JH7110_UART5_CLK_APB)));
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clk_dm(JH7110_UART5_CLK_CORE,
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- starfive_clk_gate(priv->sys,
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- "u5_dw_uart_clk_core", "perh_root",
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- SYS_OFFSET(JH7110_UART5_CLK_CORE)));
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+ starfive_clk_gate_divider(priv->sys,
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+ "u5_dw_uart_clk_core", "perh_root",
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+ SYS_OFFSET(JH7110_UART5_CLK_CORE), 8));
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clk_dm(JH7110_STG_APB,
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starfive_clk_fix_factor(priv->stg,
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