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@@ -8,6 +8,7 @@
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#include <common.h>
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#include <div64.h>
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+#include <dm.h>
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#include <pwm.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/io.h>
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@@ -24,18 +25,12 @@ int pwm_init(int pwm_id, int div, int invert)
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return 0;
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}
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-int pwm_config(int pwm_id, int duty_ns, int period_ns)
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+int pwm_config_internal(struct pwm_regs *pwm, unsigned long period_cycles,
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+ unsigned long duty_cycles, unsigned long prescale)
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{
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- struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
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- unsigned long period_cycles, duty_cycles, prescale;
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u32 cr;
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- if (!pwm)
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- return -1;
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-
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- pwm_imx_get_parms(period_ns, duty_ns, &period_cycles, &duty_cycles,
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- &prescale);
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-
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+ writel(0, &pwm->ir);
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cr = PWMCR_PRESCALER(prescale) |
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PWMCR_DOZEEN | PWMCR_WAITEN |
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PWMCR_DBGEN | PWMCR_CLKSRC_IPG_HIGH;
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@@ -48,6 +43,20 @@ int pwm_config(int pwm_id, int duty_ns, int period_ns)
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return 0;
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}
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+int pwm_config(int pwm_id, int duty_ns, int period_ns)
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+{
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+ struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
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+ unsigned long period_cycles, duty_cycles, prescale;
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+
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+ if (!pwm)
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+ return -1;
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+
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+ pwm_imx_get_parms(period_ns, duty_ns, &period_cycles, &duty_cycles,
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+ &prescale);
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+
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+ return pwm_config_internal(pwm, period_cycles, duty_cycles, prescale);
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+}
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+
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int pwm_enable(int pwm_id)
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{
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struct pwm_regs *pwm = (struct pwm_regs *)pwm_id_to_reg(pwm_id);
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@@ -68,3 +77,86 @@ void pwm_disable(int pwm_id)
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clrbits_le32(&pwm->cr, PWMCR_EN);
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}
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+
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+#if defined(CONFIG_DM_PWM)
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+struct imx_pwm_priv {
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+ struct pwm_regs *regs;
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+ bool invert;
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+};
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+
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+static int imx_pwm_set_invert(struct udevice *dev, uint channel,
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+ bool polarity)
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+{
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+ struct imx_pwm_priv *priv = dev_get_priv(dev);
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+
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+ debug("%s: polarity=%u\n", __func__, polarity);
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+ priv->invert = polarity;
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+
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+ return 0;
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+}
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+
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+static int imx_pwm_set_config(struct udevice *dev, uint channel,
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+ uint period_ns, uint duty_ns)
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+{
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+ struct imx_pwm_priv *priv = dev_get_priv(dev);
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+ struct pwm_regs *regs = priv->regs;
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+ unsigned long period_cycles, duty_cycles, prescale;
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+
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+ debug("%s: Config '%s' channel: %d\n", __func__, dev->name, channel);
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+
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+ pwm_imx_get_parms(period_ns, duty_ns, &period_cycles, &duty_cycles,
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+ &prescale);
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+
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+ return pwm_config_internal(regs, period_cycles, duty_cycles, prescale);
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+};
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+
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+static int imx_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
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+{
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+ struct imx_pwm_priv *priv = dev_get_priv(dev);
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+ struct pwm_regs *regs = priv->regs;
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+
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+ debug("%s: Enable '%s' state: %d\n", __func__, dev->name, enable);
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+
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+ if (enable)
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+ setbits_le32(®s->cr, PWMCR_EN);
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+ else
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+ clrbits_le32(®s->cr, PWMCR_EN);
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+
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+ return 0;
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+};
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+
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+static int imx_pwm_ofdata_to_platdata(struct udevice *dev)
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+{
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+ struct imx_pwm_priv *priv = dev_get_priv(dev);
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+
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+ priv->regs = (struct pwm_regs *)devfdt_get_addr(dev);
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+
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+ return 0;
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+}
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+
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+static int imx_pwm_probe(struct udevice *dev)
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+{
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+ return 0;
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+}
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+
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+static const struct pwm_ops imx_pwm_ops = {
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+ .set_invert = imx_pwm_set_invert,
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+ .set_config = imx_pwm_set_config,
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+ .set_enable = imx_pwm_set_enable,
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+};
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+
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+static const struct udevice_id imx_pwm_ids[] = {
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+ { .compatible = "fsl,imx27-pwm" },
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+ { }
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+};
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+
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+U_BOOT_DRIVER(imx_pwm) = {
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+ .name = "imx_pwm",
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+ .id = UCLASS_PWM,
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+ .of_match = imx_pwm_ids,
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+ .ops = &imx_pwm_ops,
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+ .ofdata_to_platdata = imx_pwm_ofdata_to_platdata,
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+ .probe = imx_pwm_probe,
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+ .priv_auto_alloc_size = sizeof(struct imx_pwm_priv),
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+};
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+#endif
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